Memory device and method of operating the same
AssigneeSK hynix Inc.
InventorHyung Jin Choi
Life of this patent
Estimating the term…
Abstract
Provided herein may be a memory device, a method of operating the same and a page buffer. The memory device may include a plurality of memory cells and a plurality of page buffers. The plurality of page buffers may be coupled to the plurality of memory cells through a plurality of bit lines. The plurality of page buffers may perform a bit line precharge operation of precharging first bit lines coupled to first memory cells, among the plurality of memory cells, to a first voltage, the bit line precharge operation being included in a memory operation of detecting threshold voltages of the first memory cells, and clamp potentials of second bit lines coupled to second memory cells, among the plurality of memory cells, to a second voltage during the memory operation.
Claims20
A memory device, comprising:
- a plurality of memory cells;
- and
- a plurality page buffers coupled to the plurality of memory cells through a plurality of bit lines, wherein the plurality of page buffers are configured to:
- perform a bit line precharge operation of precharging first bit lines coupled to first memory cells, among the plurality of memory cells, to a first voltage, the bit line precharge operation being included in a memory operation of detecting threshold voltages of the first memory cells, and
- clamp potentials of second bit lines coupled to second memory cells, among the plurality of memory cells, to a second voltage during the memory operation.
A page buffer, comprising:
- a switch coupled between a bit line and a node;
- a first precharge circuit coupled between the node and a supply voltage node, and configured to precharge the node to a first voltage based on whether a memory cell coupled to the bit line is a selected memory cell on which a memory operation is performed;
- and
- a second precharge circuit coupled between the node and the supply voltage node, and configured to clamp a potential of the node to a second voltage based on whether the memory cell is the selected memory cell.
A method of operating a memory device including a plurality of memory cells, the method comprising:
- performing a bit line precharge operation of precharging first bit lines coupled to first memory cells, among the plurality of memory cells, to a first voltage;
- precharging second bit lines coupled to second memory cells, among the plurality of memory cells, to a second voltage during the bit line precharge operation;
- performing an evaluation operation of sensing voltages of the first bit lines determined based on threshold voltages of the first memory cells after the bit line precharge operation;
- and
- clamping potentials of the second bit lines to the second voltage during the evaluation operation.
Dependencies are inferred from the claim text.