Systems and methods for adaptive self-referenced reads of memory devices
AssigneeMicron Technology, Inc.
InventorsGraziano Mirichigni, Corrado Villa
Life of this patent
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Abstract
Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.
Claims20
A memory device, comprising:
- a memory array comprising a plurality of memory cells;
- a control circuit operatively coupled to the memory array, the control circuit configured to:
- receive a read request for data;
- apply a first voltage to the memory array based on the read request, wherein a first set of memory cells of the plurality of memory cells is configured to be read as storing a first logic value based on the first voltage;
- count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage;
- apply a second voltage to the memory array based on the total number, wherein a second set of memory cells included in the plurality of memory cells is configured to be read as storing the first logic value based on the second voltage;
- and
- return the data based at least on bits stored in the first and the second set of memory cells.
A method, comprising:
- receiving, at a control circuit included in a memory device, a read request for data;
- applying a first voltage to a memory array of the memory device based on the read request, wherein a first set of memory cells of a plurality of memory cells of the memory array is configured to be read as storing a first logic value based on the first voltage;
- counting a total number of the plurality of memory cells that have switched to an active read state based on the first voltage;
- applying a second voltage to the memory array based on the total number, wherein a second set of memory cells of the plurality of memory cells is configured to be read as storing the first logic value based on the second voltage;
- and
- returning the data based at least on bits stored in the first and the second set of memory cells.
A memory device, comprising:
- a memory array comprising a plurality of memory cells;
- a control circuit operatively coupled to the memory array, the control circuit configured to:
- receive a read request for data;
- apply a first voltage to the memory array based on the read request, wherein a first set of memory cells of the plurality of memory cells is configured to be read as storing a first logic value based on the first voltage;
- count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage;
- determine if the total number is inside of an approach range of values, a final step range of values, or a combination thereof;
- and
- apply one or more voltage steps if the total number is inside of the approach range of values and apply a single voltage step if the total number is inside of the final step range of values to return the data.
Dependencies are inferred from the claim text.