Sense amplifying circuit of semiconductor memory device for offset cancellation operation

A sense amplifying circuit, comprising:

• a first inverter having an input terminal coupled to a first bit line and an output terminal coupled to a second inner bit line;
• a second inverter having an input terminal coupled to a second bit line and an output terminal coupled to a first inner bit line;
• a first offset cancellation switch suitable for electrically coupling the first inner bit line to the second bit line during an offset cancellation operation;
• a second offset cancellation switch suitable for electrically coupling the second inner bit line to the first bit line during the offset cancellation operation;
• a first isolation switch suitable for electrically coupling the first inner bit line to the first bit line during an amplification operation;
• and
• a second isolation switch suitable for electrically coupling the second inner bit line to the second bit line during a charge sharing operation and the amplification operation, wherein the charge sharing operation includes a main charge sharing operation and a pre-biasing operation, and the first isolation switch is turned off and the second isolation switch is turned on, during the pre-biasing operation.

A sense amplifying circuit, comprising:

• a pull-up circuit including first and second pull-up transistors respectively coupled between a pull-up voltage line and first and second inner bit lines, the first and second pull-up transistors having a cross-coupled structure;
• a pull-down circuit including first and second pull-down transistors respectively coupled between a pull-down voltage line and the first and second inner bit lines;
• a first offset cancellation switch suitable for electrically coupling the first inner bit line to a second bit line during an offset cancellation operation;
• a second offset cancellation switch suitable for electrically coupling the second inner bit line to a first bit line during the offset cancellation operation;
• a first isolation switch suitable for electrically coupling the first inner bit line to the first bit line during an amplification operation;
• a second isolation switch suitable for electrically coupling the second inner bit line to the second bit line during the amplification operation;
• a first pre-biasing switch suitable for electrically coupling a gate of the second pull-down transistor to the first bit line during the offset cancellation operation, a charge sharing operation and the amplification operation;
• and
• a second pre-biasing switch suitable for electrically coupling a gate of the first pull-down transistor to the second bit line during the offset cancellation operation and the amplification operation.

An operating method of a semiconductor memory device, the operating method comprising performing:

• a precharge operation of precharging target and reference bit lines to a precharge level;
• a charge sharing operation of making the target bit line share a charge stored in a target memory cell for the target bit line to have a voltage level different from the reference bit line;
• a pre-biasing operation of adjusting the voltage level of the reference bit line to an inverted voltage level of the target bit line;
• and
• an amplification operation of amplifying a voltage difference between the target and reference bit lines.