Column selector architecture with edge mat optimization
AssigneeMicron Technology, Inc.
InventorsYuan He, Hiroshi Akamatsu
Life of this patent
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Abstract
A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.
Claims20
An electronic device comprising:
- a section decoder configured to determine one of a first section and a second section of a memory bank for a location of a target memory cell based on a row address of the target memory cell, wherein a column decoder is disposed between the first section and the second section, and wherein the first section comprises at least two edge memory mats and at least one inner memory mat, and wherein the first section is adjacent to a bank controller of the memory bank;
- and
- a mode register configured to identify a mode of a speed of a column select operation, wherein the mode includes high or low,
- and wherein the electronic device is configured to select a voltage level to drive the column decoder based on the mode of the speed and the location of the target memory cell,
- and wherein the electronic device is configured to determine a process corner for the column select operation.
A method comprising:
- determining a location of a target memory cell based on a row address of the target memory cell, wherein the location is one of a first section and a second section of a memory bank, wherein a column decoder is disposed between the first section and the second section, and wherein the first section comprises at least two edge memory mats and at least one inner memory mat, and wherein the first section is adjacent to a bank controller of the memory bank;
- identifying a mode of a speed of a column select operation to be performed on the column decoder, wherein the mode includes high or low;
- determining a process corner for the column select operation;
- and
- selecting a voltage level to drive the column decoder based on the mode of the speed and the location of the target memory cell.
A method comprising:
- determining a process corner of a column select operation;
- identifying a voltage level corresponding to the process corner;
- and
- driving a column decoder via the voltage level, wherein the column decoder is disposed between a first section of a memory bank and a second section of the memory bank, wherein the first section comprises at least two edge memory mats and at least one inner memory mat, and wherein the first section is adjacent to a bank controller of the memory bank.
Dependencies are inferred from the claim text.