DRAM memory

A DRAM memory, comprising:

• a substrate;
• a plurality of memory banks arranged in rows and columns on the substrate;
• and
• a circuit area arranged between two adjacent columns of the plurality of memory banks, wherein the circuit area comprises a control circuit and a data transmission circuit;
• wherein the circuit area of the control circuit and the data transmission circuit has long sides and short sides, wherein the long sides are parallel to the column direction, and the short sides are parallel to the row direction;
• wherein each of the plurality of memory banks at each of the long sides of the circuit area of the control circuit and the data transmission circuit is divided into three memory blocks in a column direction, wherein the three memory blocks are arranged in parallel to each other and configured to be perpendicular to the long sides of the circuit area, and wherein each of the three memory blocks comprises memory cells arranged in rows and columns;
• wherein the control circuit and the data transmission circuit are configured to connect to a corresponding memory cell in each of the three memory blocks;
• and
• wherein each of the plurality of memory banks comprises two row decoding circuits and three column decoding circuits, wherein both a first and a second row decoding circuits of the two row decoding circuits share a same length which is perpendicular to the long sides of the circuit area, and wherein the three column decoding circuits comprise a first, a second and a third column decoding circuits arranged in each of the three memory blocks respectively.