Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell

An apparatus comprising:

• a node;
• a plurality of capacitors coupled to the node, wherein an individual capacitor of the plurality of capacitors comprises non-linear polar material;
• a select transistor coupled to the node and a bit-line, wherein the select transistor is controllable by a word-line;
• a plurality of switches coupled to the plurality of capacitors, wherein an individual switch is controllable by an individual control;
• a plurality of plate-lines coupled to the plurality of switches, wherein an individual plate-line is coupled to the individual switch;
• and
• one or more circuitries to boost the word-line above a voltage supply level during a write operation, wherein the one or more circuitries is to control the individual control, the individual plate-line, and the bit-line during the write operation.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a communication interface to allow the processor circuitry to communicate with another device;
• and
• a memory coupled to the processor circuitry, wherein the memory comprises:
• a node;
• a first capacitor comprising non-linear polar material, the first capacitor having a first terminal coupled to the node;
• a second capacitor comprising the non-linear polar material, the second capacitor having a first terminal coupled to the node;
• a select transistor coupled to the node and a bit-line, wherein the select transistor is controllable by a word-line;
• a first switch coupled to the first capacitor and a first plate-line, the first switch controllable by a first control;
• a second switch coupled to the second capacitor and a second plate-line, the second switch controllable by a second control;
• and
• one or more circuitries to boost the word-line above a voltage supply level during a write operation, wherein the one or more circuitries is to control the first plate-line, the second plate-line, the first control, the second control, and the bit-line during the write operation.