Apparatus and methods for fractional synchronization using direct digital frequency synthesis

A method for direct digital frequency synthesis, the method comprising:

• sequentially writing a digital desired pattern into a memory with N addresses;
• continually sequentially reading the digital desired pattern using a memory operating frequency clock, the memory operating frequency clock based on a sampling frequency clock which is used for high-speed data processing;
• processing a readout digital desired pattern into an analog representation with a desired duty cycle;
• and
• outputting a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.

A device comprising:

• a memory with N addresses;
• a port configured to sequentially write a digital desired pattern with M periods into the N addresses;
• the port configured to continually readout in sequence the digital desired pattern from the N addresses at a memory operating frequency clock, wherein the memory operating frequency clock is divided down from a clock used for high-speed data processing;
• and
• an analog signal processing circuit configured to output an analog synthesized frequency clock with a defined duty cycle from the readout digital desired pattern to a digital core, wherein the analog synthesized frequency clock is fractionally synchronized with the clock and a rate of the analog synthesized frequency clock is determined from the N addresses, the M periods, and the clock.