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US 11,538,509 B2Granted
Compute-in-memory with ternary activation
AssigneeQUALCOMM Incorporated
InventorsSeyed Arash Mirhaj, Ankit Srivastava, Sameer Wadhwa, Ren Li, Suren Mohan
Life of this patent
Estimating the term…
Abstract
A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.
Claims25
A memory, comprising:
- a bitcell having a pair of switches connected to an output node;
- a capacitor coupled to the output node;
- a first storage element and a plurality of additional storage elements;
- and
- controller configured to select a first bit from the first storage element to control the pair of switches responsive to the first bit during a first phase of operation for the memory and configured to select a second bit from the plurality of additional storage elements to control the pair of switches responsive to the second bit during a second phase of operation for the memory,
- wherein the controller is further configured during the first phase of operation to close a first switch in the pair of switches and to open a second switch in the pair of switches responsive to the first bit having a first binary value and to open the first switch and to close the second switch responsive to the first bit having a second binary value that is a complement of the first binary value, and
- wherein the controller is further configured during the second phase of operation to reverse a switching state of the first switch and the second switch responsive to the second bit having the first binary value and to maintain a switching state of the first switch and the second switch responsive to the second bit having the second binary value.
4 more elements
A memory, comprising:
- a bitcell having a pair of switches connected to an output node, wherein the bitcell comprises a first inverter that is cross-coupled with a second inverter, and wherein the pair of switches includes a first switch coupled between an output node of the first inverter and the output node and includes a second switch coupled between an output node of the second inverter and the output node;
- a capacitor coupled to the output node;
- a first storage element and a plurality of additional storage elements;
- and
- controller configured to select a first bit from the first storage element to control the pair of switches responsive to the first bit during a first phase of operation for the memory and configured to select a second bit from the plurality of additional storage elements to control the pair of switches responsive to the second bit during a second phase of operation for the memory, and
- a third switch coupled between the output node and ground.
3 more elements
A method of controlling a bitcell to multiply a stored bit with a signed input bit, comprising:
- during a first phase of operation and responsive to a sign of the signed input bit having a first binary value, closing a first switch that is coupled between a node for the stored bit and an output node and opening a second switch that is coupled between a node for a complement of the stored bit and the output node;
- during the first phase of operation and responsive to the sign of the signed bit having a second binary value, opening the first switch and closing the second switch;
- during a second phase of operation and responsive to a magnitude of the signed input bit having the first binary value, reversing a switching state of the first switch and the second switch established during the first phase of operation;
- and
- during the second phase of operation and responsive to the magnitude of the signed input bit having the second binary value, maintaining the switching state of the first switch and the second switch established during the first phase of operation.
2 more elements
A memory, comprising:
- a bitcell configured to store a stored bit, the bitcell including a first switch coupled between a node for the stored bit and an output node and a second switch coupled between a node for a complement of the stored bit and the output node;
- a capacitor having a first plate connected to the output node;
- a controller configured to open the second switch and to close the first switch responsive to a sign of an input word having a first binary value and to open the first switch and to close the second switch responsive to the sign of the input word having a second binary value to control a switching state of the first switch and of the second switch during a first phase of operation, wherein the second binary value is a complement of the first binary value;
- and
- an input buffer for storing the input word, wherein the controller is further configured during a second phase of operation to reverse the switching state of the first switch and of the second switch responsive to a selected magnitude bit in the input buffer having the first binary value.
2 more elements
A method of operation for a compute-in-memory, comprising:
- during a first phase of operation, controlling a pair of switches coupled between a bitcell and a plate of a capacitor responsive to a sign bit;
- during a second phase of operation controlling the pair of switches responsive to a magnitude bit;
- wherein controlling the pair of switches during the first phase of operation comprises closing a first switch in the pair of switches and opening a second switch in the pair of switches responsive to the sign bit having a first binary value;
- and
- wherein controlling the pair of switches during the first phase of operation further comprises opening the first switch and closing the second switch responsive to the sign bit having a second binary value that is a complement of the first binary value.
2 more elements
Dependencies are inferred from the claim text.