Header circuit placement in memory device

An integrated circuit comprising:

• a semiconductor layer including:
• a first region corresponding to a circuit array,
• a second region corresponding to a set of interface circuits to operate the circuit array, wherein a side of the first region faces a first side of the second region along a first direction, and
• a third region corresponding to a set of header circuits to provide power to the set of interface circuits through a set of metal rails extending along a second direction traversing the first direction, wherein a side of the third region faces a second side of the second region along the second direction,
• wherein the first side of the second region extending along the second direction is shorter than the second side of the second region extending along the first direction,
• wherein the set of metal rails extending along the second direction is shorter than the first side of the second region.

An integrated circuit comprising:

• a semiconductor layer including:
• a first region corresponding to a circuit array,
• a second region corresponding to a set of interface circuits to operate the circuit array, wherein a side of the first region faces a first side of the second region along a first direction, and
• a third region corresponding to a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction, wherein a side of the third region faces a second side of the second region along the second direction,
• wherein the set of header circuits includes:
• a first header circuit to provide a first voltage to a first subset of the set of interface circuits, and
• a switch rail header circuit to selectively provide one of the first voltage or a second voltage to a second subset of the set of interface circuits, wherein the first header circuit and the switch rail header circuit share a well structure.