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US 11,538,432 B2Granted
Output buffer increasing slew rate of output signal voltage without increasing current consumption
AssigneeDB HiTek Co., Ltd.
InventorsHak Jin Jung, Eun Ji Youn, Pyung Sik Ma
Life of this patent
Estimating the term…
Abstract
An input stage configured to differentially amplify an input signal and an output signal, a first current mirror and a second current mirror configured to receive a differential current from the input stage, an output stage including first and second output transistors, respectively including a gate connected to the first and second current mirrors, and a slew rate compensation circuit configured to (i) mirror a comparison current generated by comparing a voltage of a first input signal with a voltage of a second input signal, and (ii) provide the mirrored comparison current to the gate of the first or second output transistor.
Claims20
An output buffer comprising:
- an input stage including a first amplifier generating first and second currents by differentially amplifying a first input signal and a second input signal, and a second amplifier generating third and fourth currents by differentially amplifying the first input signal and the second input signal;
- a first current mirror including first and second transistors connected in series at a first node configured to receive or provide the first current and connected between a first power source and a second node, and third and fourth transistors connected in series at a third node configured to receive or provide the second current and connected between the first power source and a fourth node;
- a second current mirror including fifth and sixth transistors connected in series at a fifth node configured to receive or provide the third current and connected between a second power source and a sixth node, and seventh and eighth transistors connected in series at a seventh node configured to receive or provide the fourth current and connected between the second power source and an eighth node;
- an output stage including a first output transistor including a gate connected to the fourth node and connected between the first power source and an output node, and a second output transistor including a gate connected to the eighth node and connected between the second power source and the output node;
- and
- a slew rate compensation circuit configured to mirror a comparison current generated by comparing a voltage of the first input signal with a voltage of the second input signal, and provide a first mirrored comparison current to at least one of the fourth node or the eighth node,
- wherein the slew rate compensation circuit is configured to generate a first comparison current between the first power source and the output node, generate a first mirroring current and a second mirroring current resulting from mirroring the first comparison current, provide the first mirroring current to the eighth node, and provide the second mirroring current to the seventh node.
4 more elements
An output buffer comprising:
- an input stage including a first amplifier generating first and second currents by differentially amplifying a first input signal and a second input signal, and a second amplifier generating third and fourth currents by differentially amplifying the first input signal and the second input signal;
- a first current mirror including first and second transistors connected in series at a first node configured to receive or provide the first current and connected between a first power source and a second node, and third and fourth transistors connected in series at a third node configured to receive or provide the second current and connected between the first power source and a fourth node;
- a second current mirror including fifth and sixth transistors connected in series at a fifth node configured to receive or provide the third current and connected between a second power source and a sixth node, and seventh and eighth transistors connected in series at a seventh node configured to receive or provide the fourth current and connected between the first power source and an eighth node;
- an output stage including a first output transistor including a gate connected to the fourth node and connected between the first power source and an output node, and a second output transistor including a gate connected to the eighth node and connected between the second power source and the output node;
- and
- a slew rate compensation circuit configured to mirror a comparison current generated by comparing a voltage of the first input signal with a voltage of the second input signal, and provide a first mirrored comparison current to at least one of the fourth node or the eighth node,
- wherein the slew rate compensation circuit is configured to generate a first comparison current between the first power source and the output node, generate a first mirroring current and a second mirroring current resulting from mirroring the first comparison current, provide the first mirroring current to the fourth node, and provide the second mirroring current to the seventh node.
4 more elements
An output buffer comprising:
- an input stage including a first amplifier generating first and second currents by differentially amplifying a first input signal and a second input signal, and a second amplifier generating third and fourth currents by differentially amplifying the first input signal and the second input signal;
- a first current mirror including first and second transistors connected in series at a first node configured to receive or provide the first current and connected between a first power source and a second node, and third and fourth transistors connected in series at a third node configured to receive or provide the second current and connected between the first power source and a fourth node;
- a second current mirror including fifth and sixth transistors connected in series at a fifth node configured to receive or provide the third current and connected between a second power source and a sixth node, and seventh and eighth transistors connected in series at a seventh node configured to receive or provide the fourth current and connected between the first power source and an eighth node;
- an output stage including a first output transistor including a gate connected to the fourth node and connected between the first power source and an output node, and a second output transistor including a gate connected to the eighth node and connected between the second power source and the output node;
- and
- a slew rate compensation circuit configured to mirror a comparison current generated by comparing a voltage of the first input signal with a voltage of the second input signal, and provide a first mirrored comparison current to at least one of the fourth node or the eighth node,
- wherein the slew rate compensation circuit is configured to generate a first comparison current between the first power source and the output node, generate a first mirroring current, a second mirroring current, and a third mirroring current resulting from mirroring the first comparison current, provide the first mirroring current to the eighth node, provide the second mirroring current to the fourth node, and provide the third mirroring current to the seventh node.
4 more elements
Dependencies are inferred from the claim text.