Larger backplane suitable for high speed applications

A display system operative to display information, the display system comprising:

• a backplane comprising a two-dimensional array of pixel drive circuits, wherein each pixel drive circuit comprises a memory element and circuits operative to create a pixel drive waveform responsive to a data state of the memory element, and wherein
• the array of pixel drive circuits is divided into a plurality of independent segments of pixel drive circuits, and wherein a separate row select circuit assembly is associated with each of the independent segments of pixel drive circuits, and wherein
• each row select assembly comprises a plurality of row select circuits, comprising one for each of the rows of the independent segment of pixel drive circuits with which the row select assembly is associated, wherein each row select circuit comprises a row decoder circuit and an optional word line driver, wherein the row decoder circuit is operative to detect from an input if it is the selected row, and if selected, thereby to cause a changing of its state, and further to change an output of the word line driver, thereby changing the state of the word line of the selected row to a state operative to enable the memory elements of the pixel drive circuits of that row to receive data asserted on bit lines, and wherein
• word lines of rows of a first independent segment of pixel drive circuits each pass underneath the pixel drive circuits of a second segment of pixel drive circuit without controlling the pixel drive circuits of the second segment, and wherein the word line for each row of the first independent segment of pixels must pass underneath the pixel drive circuits of the second segment to reach the pixel drive circuits of the first segment, and wherein
• the word lines of the first independent segment of pixel drive circuits are operated by a first row select assembly, and wherein the word lines of a second independent segment of pixel drive circuits are operated by a second row select assembly, and wherein
• memory elements of bit line drivers associated with the pixel drive circuits of a particular independent segment of pixel drive circuits are loaded with pixel state data state to be loaded on the memory elements of the pixel drive circuits, and wherein
• data stored on memory elements of bit line drivers associated with pixel drive circuits of a particular independent segment of the pixel drive circuits are written to a row of that independent segment of pixel drive circuits when the word line for that row of the independent segment of pixel drive circuits is pulled to a state that enables memory cells of that row to be written with the data stored on the memory elements of the bit lines drivers.