Shift register and drive method thereof, and gate drive circuit

A shift register comprising an input circuit, a reset circuit, a first output circuit, and a second output circuit,

• wherein the input circuit is coupled to an input terminal and a first node, and is configured to provide an input signal from the input terminal to the first node;
• wherein the reset circuit is coupled to a reset signal terminal, the first node, and a first voltage terminal, and is configured to provide a first voltage from the first voltage terminal to the first node under the control of a reset signal from the reset signal terminal;
• wherein the first output circuit is coupled to the first node, a first control signal terminal, a second control signal terminal, a first clock signal terminal, a second clock signal terminal, and a first output terminal, and is configured to output from the first output terminal one of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal, as a first scan signal, based on a first control signal from the first control signal terminal, a second control signal from the second control signal terminal, and a voltage of the first node;
• wherein the second output circuit is coupled to the first node, the first control signal terminal, the second control signal terminal, the first clock signal terminal, the second clock signal terminal, and a second output terminal, and is configured to output from the second output terminal the other of the first clock signal and the second clock signal, as a second scan signal, based on the first control signal, the second control signal, and the voltage of the first node,
• wherein the first output circuit comprises a third transistor, a fourth transistor, a fifth transistor, and a capacitor;
• wherein a control electrode of the third transistor is coupled to a first terminal of the capacitor and the first node, wherein a first electrode of the third transistor is coupled to a second electrode of the fourth transistor and a second electrode of the fifth transistor, and wherein a second electrode of the third transistor is coupled to a second terminal of the capacitor and the first output terminal;
• wherein a control electrode of the fourth transistor is coupled to the first control signal terminal, and wherein a first electrode of the fourth transistor is coupled to the first clock signal terminal;
• wherein a control electrode of the fifth transistor is coupled to the second control signal terminal, and wherein a first electrode of the fifth transistor is coupled to the second clock signal terminal;
• wherein the second output circuit comprises a sixth transistor, a seventh transistor, and an eighth transistor;
• wherein a control electrode of the sixth transistor is coupled to the first node, wherein a first electrode of the sixth transistor is coupled to a second electrode of the seventh transistor and a second electrode of the eighth transistor, and wherein a second electrode of the sixth transistor is coupled to the second output terminal;
• wherein a control electrode of the seventh transistor is coupled to the first control signal terminal, and wherein a first electrode of the seventh transistor is coupled to the second clock signal terminal;
• wherein a control electrode of the eighth transistor is coupled to the second control signal terminal, and wherein a first electrode of the eighth transistor is coupled to the first clock signal terminal;
• wherein when the first output circuit outputs the first clock signal as the first scan signal, the second output circuit outputs the second clock signal as the second scan signal;
• and
• wherein when the first output circuit outputs the second clock signal as the first scan signal, the second output circuit outputs the first clock signal as the second scan signal.