Light emission control shift register and method thereof, gate driving circuit, and display device

A light emission control shift register, comprising:

• an input circuit electrically connected to a signal input terminal, a first clock signal terminal and a first node;
• wherein the input circuit is configured to output a signal of the signal input terminal to the first node under the control of a signal from the first clock signal terminal;
• a first control circuit electrically connected to the first node, a second clock signal terminal, a third clock signal terminal, a first voltage terminal, a second voltage terminal and a second node;
• wherein the first control circuit is configured to output a voltage of the first voltage terminal to the second node under the control of a signal from the first node;
• the first control circuit is further configured to transmit a voltage of the second voltage terminal to the second node under the control of signals from the second clock signal terminal and the third clock signal terminal;
• a second control circuit electrically connected to the first node, the second node, a third node, the first voltage terminal and the second voltage terminal;
• wherein the second control circuit is configured to transmit the voltage of the first voltage terminal to the third node under the control of a signal from the second node and the first voltage terminal;
• the second control circuit is further configured to transmit the voltage of the second voltage terminal to the third node under the control of the signal from the first node;
• a third control circuit electrically connected to the third node, a fourth node, the first voltage terminal, the second voltage terminal, the first clock signal terminal and the third clock signal terminal;
• wherein the third control circuit is configured to transmit the voltage of the first voltage terminal to the fourth node under the control of a signal from the third node;
• the third control circuit is further configured to transmit the voltage of the second voltage terminal to the fourth node under the control of the signals from the first clock signal terminal and the third clock signal terminal;
• a fourth control circuit electrically connected to the fourth node, the first node, the first voltage terminal, the second voltage terminal and a signal output terminal;
• wherein the fourth control circuit is configured to transmit the voltage of the first voltage terminal to the signal output terminal under the control of the signal from the first node;
• the fourth control circuit is further configured to transmit the voltage of the second voltage terminal to the signal output terminal under the control of a signal from the fourth node.