Shift register circuit and method of driving the same, gate driver circuit, and display apparatus

A shift register circuit, comprising:

• a first input sub-circuit coupled to a first signal input terminal, a second signal input terminal and a pull-up node, the first input sub-circuit being configured to transmit a signal received at the second signal input terminal to the pull-up node under control of a signal received at the first signal input terminal;
• an output sub-circuit at least coupled to the pull-up node, a first clock signal terminal, an output signal transmission terminal, a shift signal output terminal and a first scan signal output terminal, the output sub-circuit being configured to transmit a signal received at the first clock signal terminal to the shift signal output terminal and to transmit a signal received at the output signal transmission terminal to the first scan signal output terminal in response to a voltage of the pull-up node;
• an output control sub-circuit coupled to a second clock signal terminal, a chamfering signal terminal and the first scan signal output terminal, the output control sub-circuit being configured to transmit a signal received at the chamfering signal terminal to the first scan signal output terminal in response to a signal received at the second clock signal terminal in a predetermined time before the first scan signal output terminal stops outputting the signal from the output signal transmission terminal;
• a second input sub-circuit coupled to a control signal terminal, the first signal input terminal and a first node, the second input sub-circuit being configured to transmit the signal received at the first signal input terminal to the first node under control of a signal received at the control signal terminal;
• a compensation sub-circuit coupled to a fifth clock signal terminal, the first node and the pull-up node, the compensation sub-circuit being configured to transmit a signal received at the fifth clock signal terminal to the pull-up node under control of a voltage of the first node and the signal received at the fifth clock signal terminal;
• a storage sub-circuit coupled to a sixth voltage terminal and the first node, the storage sub-circuit being configured to store a signal that is transmitted to the first node from the first signal input terminal;
• a first potential boosting sub-circuit coupled to a seventh voltage terminal, the pull-up node and a second node, the first potential boosting sub-circuit being configured to transmit a voltage of the seventh voltage terminal to the second node under control of the voltage of the pull-up node;
• wherein the second node is coupled to the compensation sub-circuit and
• a second potential boosting sub-circuit coupled to the seventh voltage terminal, the first node and the second input sub-circuit, the second potential boosting sub-circuit being configured to transmit the voltage of the seventh voltage terminal to the second input sub-circuit under the control of the voltage of the first node;
• wherein the chamfering signal terminal is configured to transmit a signal with a voltage amplitude within a variation range of a voltage amplitude of a signal of the first scan signal output terminal.