Clock and voltage generation circuit and display device including the same

A display device comprising:

• a display panel including a plurality of pixels connected to a plurality of scan lines and a plurality of data lines;
• a gate driver which receives a first gate clock signal and a second gate clock signal and drives the plurality of scan lines;
• a data driver which drives the plurality of data lines;
• a clock and voltage generation circuit which receives a kickback signal and a gate pulse signal;
• and
• a timing controller which controls the gate driver and the data driver, and provides the gate pulse signal and the kickback signal to the clock and voltage generation circuit,
• wherein the clock and voltage generation circuit comprises:
• a voltage generator which generates a first gate high voltage, a first gate low voltage, a second gate high voltage, and a second gate low voltage;
• a first level shifter which receives the first gate high voltage and the first gate low voltage from the voltage generator and generates the first gate clock signal which swings between the first gate high voltage and the first gate low voltage in synchronization with the gate pulse signal;
• and
• a second level shifter which receives the second gate high voltage and the second gate low voltage from the voltage generator and generates the second clock signal which swings between the second gate high voltage and the second gate low voltage in synchronization with the gate pulse signal,
• wherein the clock and voltage generation circuit lowers the second gate high voltage to a voltage level of a kickback reference voltage in response to the kickback signal,
• wherein the first gate high voltage and the second gate high voltage are different voltage levels from each other.