US 11,538,397 B2 · First shift register, driving method thereof, gate driving circuit, and display device

Abstract

Disclosed are a first shift register, a driving method for the same, a gate driving circuit and a display device. The first shift register includes a first unit, M second units and N third units. A first signal output terminal of the first unit is connected with M second signal input terminals of the M second units. A second signal output terminal of each second unit is connected with third signal input terminals of N/M third units respectively. The first unit outputs a voltage of a first clock signal terminal to the first signal output terminal and a fourth signal output terminal under the control of a first signal input terminal and a second clock signal terminal and outputs a voltage of a first voltage terminal to the first signal output terminal and the fourth signal output terminal.

Drawings

Claims15

Dependent claims

A first shift register, comprising:

a first unit, M second units and N third units, wherein M and N are positive integers, N is an integral multiple of M, 2≤M, and 2≤N/M;
wherein the first unit is connected with a first signal input terminal, a first clock signal terminal, a second clock signal terminal, a first voltage terminal, a first reset signal terminal, a first signal output terminal and a fourth signal output terminal respectively and arranged to output a voltage of the first clock signal terminal to the first signal output terminal and the fourth signal output terminal under control of the first signal input terminal and the second clock signal terminal and output a voltage of the first voltage terminal to the first signal output terminal and the fourth signal output terminal under control of the first reset signal terminal and the second clock signal terminal;
a second unit is connected with a second signal input terminal, a second signal output terminal and a control clock signal terminal respectively and arranged to output a voltage of the control clock signal terminal to the second signal output terminal under control of the second signal input terminal;
a third unit is connected with an output clock signal terminal, a third signal input terminal and a third signal output terminal respectively and arranged to output a voltage of the output clock signal terminal to the third signal output terminal under control of the third signal input terminal;
and
the first signal output terminal of the first unit in the first shift register is connected with the M second signal input terminals of the M second units;
the second signal output terminal of each second unit is connected with the third signal input terminals of N/M third units respectively, and different second signal output terminals are connected with different third signal input terminals;
and different second units are connected with different control clock signal terminals, and different third units are connected with different output clock signal terminals;
wherein the first unit comprises an input module, an energy storage module, a first output module, a first reset module, a pull-down control module and a pull-down module;
the input module is connected with the first signal input terminal, the second clock signal terminal and a pull-up node and arranged to output a signal of the first signal input terminal to the pull-up node under control of the second clock signal terminal;
the energy storage module is connected with the pull-up node and arranged to store a voltage of the pull-up node or charge the pull-up node;
the first output module is connected with the pull-up node, the first clock signal terminal, the first signal output terminal and the fourth signal output terminal and arranged to output a signal of the first clock signal terminal to the first signal output terminal and the fourth signal output terminal under control of the pull-up node;
the first reset module is connected with the first reset signal terminal, the first voltage terminal and the pull-up node and arranged to output the voltage of the first voltage terminal to the pull-up node under control of the first reset signal terminal;
the pull-down control module is connected with the second clock signal terminal, the first voltage terminal, the pull-up node and a pull-down node and arranged to output a signal of the second clock signal terminal to the pull-down node under control of the second clock signal terminal, the first voltage terminal and the pull-up node;
and
the pull-down module is connected with the pull-down node, the first voltage terminal, the first signal output terminal and the fourth signal output terminal and arranged to output the voltage of the first voltage terminal to the first signal output terminal and the fourth signal output terminal under control of the pull-down node.

13 more elements

A gate driving circuit, comprising two gate driving units, wherein

one gate driving unit of the two gate driving units comprises at least two stages of cascaded first shift registers, and the first shift register comprises a first unit, M second units and N third units, wherein M and N are positive integers, N is an integral multiple of M, 2≤M, and 2≤N/M;
the first unit is connected with a first signal input terminal, a first clock signal terminal, a second clock signal terminal, a first voltage terminal, a first reset signal terminal, a first signal output terminal and a fourth signal output terminal respectively and arranged to output a voltage of the first clock signal terminal to the first signal output terminal and the fourth signal output terminal under control of the first signal input terminal and the second clock signal terminal and output a voltage of the first voltage terminal to the first signal output terminal and the fourth signal output terminal under control of the first reset signal terminal and the second clock signal terminal;
a second unit is connected with a second signal input terminal, a second signal output terminal and a control clock signal terminal respectively and arranged to output a voltage of the control clock signal terminal to the second signal output terminal under control of the second signal input terminal;
a third unit is connected with an output clock signal terminal, a third signal input terminal and a third signal output terminal respectively and arranged to output a voltage of the output clock signal terminal to the third signal output terminal under control of the third signal input terminal;
the first signal output terminal of the first unit in the first shift register is connected with the M second signal input terminals of the M second units;
the second signal output terminal of each second unit is connected with third signal input terminals of N/M third units respectively, and different second signal output terminals are connected with different third signal input terminals;
different second units are connected with different control clock signal terminals, and different third units are connected with different output clock signal terminals;
the other gate driving unit of the two gate driving units comprises at least two stages of cascaded second shift registers, and the second shift register comprises a fourth unit, M second units and N third units, wherein the fourth unit is connected with a first signal input terminal, a first clock signal terminal, a second clock signal terminal, a first voltage terminal, a first reset signal terminal and a first signal output terminal respectively and arranged to output a voltage of the first clock signal terminal to the first signal output terminal under control of the second clock signal terminal and output a voltage of the first voltage terminal to the first signal output terminal under control of the first reset signal terminal and the second clock signal terminal;
the first signal output terminal of the fourth unit is connected with M second signal input terminals of the M second units;
third signal output terminals in the gate driving unit are arranged to be connected with gate lines which are sequentially arranged, the gate lines being divided into different gate line groups with each comprising N gate lines;
one gate driving unit of the two gate driving units is connected with the gate lines in odd gate line groups which are sequentially arranged, while the other gate driving unit of the two gate driving units is connected with the gate lines in even gate line groups which are sequentially arranged;
and
in each gate driving unit:
a first signal input terminal of a first-stage shift register is connected with an initial signal terminal,
a first signal input terminal of the shift register of any stage except the first-stage shift register is connected with a first signal output terminal of a previous-stage shift register of the shift register of a present stage, and
a first reset signal terminal of the shift register of any stage except a last-stage shift register is connected with a first signal output terminal of a next-stage shift register of the shift register of the present stage;
wherein the first unit comprises an input module, an energy storage module, a first output module, a first reset module, a pull-down control module and a pull-down module;
the input module is connected with the first signal input terminal, the second clock signal terminal and a pull-up node and arranged to output a signal of the first signal input terminal to the pull-up node under control of the second clock signal terminal;
the energy storage module is connected with the pull-up node and arranged to store a voltage of the pull-up node or charge the pull-up node;
the first output module is connected with the pull-up node, the first clock signal terminal, the first signal output terminal and the fourth signal output terminal and arranged to output a signal of the first clock signal terminal to the first signal output terminal and the fourth signal output terminal under control of the pull-up node;
the first reset module is connected with the first reset signal terminal, the first voltage terminal and the pull-up node and arranged to output the voltage of the first voltage terminal to the pull-up node under control of the first reset signal terminal;
the pull-down control module is connected with the second clock signal terminal, the first voltage terminal, the pull-up node and a pull-down node and arranged to output a signal of the second clock signal terminal to the pull-down node under control of the second clock signal terminal, the first voltage terminal and the pull-up node;
and
the pull-down module is connected with the pull-down node, the first voltage terminal, the first signal output terminal and the fourth signal output terminal and arranged to output the voltage of the first voltage terminal to the first signal output terminal and the fourth signal output terminal under control of the pull-down node.

21 more elements

A display device, comprising a gate driving circuit which comprises two gate driving units, wherein

one gate driving unit of the two gate driving units comprises at least two stages of cascaded first shift registers, and the first shift register comprises a first unit, M second units and N third units, wherein M and N are positive integers, N is an integral multiple of M, 2≤M, and 2≤N/M;
the first unit is connected with a first signal input terminal, a first clock signal terminal, a second clock signal terminal, a first voltage terminal, a first reset signal terminal, a first signal output terminal and a fourth signal output terminal respectively and arranged to output a voltage of the first clock signal terminal to the first signal output terminal and the fourth signal output terminal under control of the first signal input terminal and the second clock signal terminal and output a voltage of the first voltage terminal to the first signal output terminal and the fourth signal output terminal under control of the first reset signal terminal and the second clock signal terminal;
a second unit is connected with a second signal input terminal, a second signal output terminal and a control clock signal terminal respectively and arranged to output a voltage of the control clock signal terminal to the second signal output terminal under control of the second signal input terminal;
a third unit is connected with an output clock signal terminal, a third signal input terminal and a third signal output terminal respectively and arranged to output a voltage of the output clock signal terminal to the third signal output terminal under control of the third signal input terminal;
the first signal output terminal of the first unit in the first shift register is connected with M second signal input terminals of the M second units;
the second signal output terminal of each second unit is connected with third signal input terminals of N/M third units respectively, and different second signal output terminals are connected with different third signal input terminals;
different second units are connected with different control clock signal terminals, and different third units are connected with different output clock signal terminals;
the other gate driving unit of the two gate driving units comprises at least two stages of cascaded second shift registers, and the second shift register comprises a fourth unit, M second units and N third units, wherein the fourth unit is connected with a first signal input terminal, a first clock signal terminal, a second clock signal terminal, a first voltage terminal, a first reset signal terminal and a first signal output terminal respectively and arranged to output a voltage of the first clock signal terminal to the first signal output terminal under control of the second clock signal terminal and output a voltage of the first voltage terminal to the first signal output terminal under control of the first reset signal terminal and the second clock signal terminal;
the first signal output terminal of the fourth unit is connected with M second signal input terminals of the M second units;
third signal output terminals in the gate driving unit are arranged to be connected with gate lines which are sequentially arranged, the gate lines being divided into different gate line groups with each comprising N gate lines;
one of the two gate driving units is connected with the gate lines in odd gate line groups which are sequentially arranged, while the other is connected with the gate lines in even gate line groups which are sequentially arranged;
and
in each gate driving unit:
a first signal input terminal of a first-stage shift register is connected with an initial signal terminal,
a first signal input terminal of the shift register of any stage except the first-stage shift register is connected with a first signal output terminal of a previous-stage shift register of the shift register of present stage, and
a first reset signal terminal of the shift register of any stage except a last-stage shift register is connected with a first signal output terminal of a next-stage shift register of the shift register of the present stage;
the display device further comprises a backlight module and a driver Integrated Circuit (IC);
the backlight module comprises a plurality of point light sources which are arranged in an array;
the driver IC is arranged to provide a channel driving signal for the point light sources;
and the fourth signal output terminal is arranged to provide a reset driving signal for the point light sources.

17 more elements

Dependencies are inferred from the claim text.

Description13,637 words

Summary2,476 words

#The present application claims the priority of Chinese patent application No. 202011449221.9, filed to the CNIPA on Dec. 9, 2020, the contents of which are hereby incorporated by reference.

#Embodiments of the present disclosure relate to, but not limited to, the field of display technologies, and particularly to a first shift register, a driving method thereof, a gate driving circuit, and a display device.

#With the constant development of display technologies, a Mini Light Emitting Diode (Mini LED) technology has gradually become a research hot spot in the field of display technologies. For example, a Mini LED may be used for a backlight module in a Liquid Crystal Display (LCD) device as an emitting element of the backlight module. Therefore, with the advantages of the Mini LED, the backlight module may achieve the advantages of local dimming, rapid response, simple structure, long service life and the like.

Brief description of the drawings12 figures

#The drawings provide an understanding to the technical solution of the present disclosure, form a part of the specification, and are adopted to explain, together with the embodiments of the present disclosure, the technical solutions of the present disclosure and not intended to form limits to the technical solutions of the present disclosure.

#FIG. 1 is a structural schematic diagram of an exemplary Mini LED array substrate.

#FIG. 2 is a schematic diagram of a conventional Mini-LED driving circuit.

Detailed description10,865 words

#The embodiments of the present disclosure will be described below in combination with the drawings in detail. The following embodiments are adopted to describe the present disclosure but not intended to limit the scope of the present disclosure. It is to be noted that the embodiments in the present disclosure and characteristics in the embodiments may be freely combined without conflicts.

#Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure should have the same meanings as commonly understood by those of ordinary skill in the art that the present disclosure belongs to. “First”, “second”, and similar terms used in the embodiments of the present disclosure do not represent any sequence, number, or significance but are only adopted to distinguish different components. “Include”, “contain”, or a similar term means that an element or object appearing before the term covers an element or object and equivalent thereof listed after the term and does not exclude other elements or objects.

#It can be understood by those skilled in the art that transistor adopted in all the embodiments of the present disclosure may be a thin film transistor, or a field-effect transistor, or another device with the same characteristic. Preferably, the thin-film transistor used in the embodiments of the present disclosure may be an oxide semiconductor transistor. A source and drain of the transistor used here are symmetric, so the drain and the source may be interchanged. In the embodiments of the present disclosure, for distinguishing the two electrodes, except the gate, of the transistor, one electrode is called a first electrode, the other electrode is called a second electrode, the first electrode may be the source or the drain, and the second electrode may be the drain or the source.

First shift register, driving method thereof, gate driving circuit, and display device

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First shift register, driving method thereof, gate driving circuit, and display device

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Abstract

Drawings

Drawings

Claims15

Description13,637 words

Drawings

Description13,637 words

Classification11 codes

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