Shift register unit and driving method thereof, gate drive circuit, and display device

A shift register unit, comprising:

• an input circuit, a first control circuit, a second control circuit and an output circuit, wherein
• the input circuit is coupled to a signal input terminal, a first power supply terminal, a first clock signal terminal, a first control node and a second control node respectively, and is configured to provide signals of the signal input terminal to the first control node under control of the first clock signal terminal, and provide signals of the first power supply terminal or the first clock signal terminal to the second control node under control of the first clock signal terminal and the first control node;
• the first control circuit is coupled to the first control node, the second control node, a second clock signal terminal, the first power supply terminal, a second power supply terminal and a first output terminal respectively, and is configured to provide signals of the second power supply terminal or the second clock signal terminal to the first output terminal under control of the first control node, the second control node and the first power supply terminal;
• the second control circuit is coupled to the first output terminal, a third clock signal terminal, a fourth clock signal terminal, the first power supply terminal and a second output terminal respectively, and is configured to provide signals of the first power supply terminal to the second output terminal under control of the first output terminal, the third clock signal terminal and the fourth clock signal terminal;
• and
• the output circuit is coupled to the first power supply terminal, the second power supply terminal, the first output terminal and the second output terminal respectively, and is configured to provide signals of the second power supply terminal to the second output terminal under control of the first output terminal, and suppress leakage of the second output terminal through the signals of the first power supply terminal,
• wherein the output circuit comprises an output sub-circuit and a leakage suppression sub-circuit, wherein
• the output sub-circuit is coupled to the first output terminal, the second power supply terminal, a third control node and the second output terminal respectively, and is configured to provide signals of the second power supply terminal to the third control node under control of the first output terminal and switch on the third control node and the second output terminal under the control of the first output terminal;
• and
• the leakage suppression sub-circuit is coupled to the first power supply terminal, the second output terminal and the third control node respectively, and is configured to provide signals of the first power supply terminal to the third control node under control of the second output terminal.