Data driving circuit and a display device including the same

A data driving circuit, comprising:

• a digital to analog converter which converts image data into analog data signals;
• output buffers which respectively output the data signals to first to k-th data lines (wherein k is an integer greater than 2);
• and
• an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are to be supplied,
• wherein output times of the data signals output from the output buffers are different due to a difference in the delay times,
• wherein the output delay controller comprises;
• a clock frequency divider which divides a frequency of a data transmission clock to generate a reference clock;
• a reference period generator which generates reference periods for delaying an output of the data signals based on a period of the reference clock;
• a minimum delay selector which selects one of the reference periods as a minimum delay value based on the position information;
• and
• a delay time determiner which determines delay times of the first to k-th transmission lines based on the minimum delay, value and a delay control signal, and delays and outputs the data signals by the delay times.

A display device, comprising:

• a display area including pixels connected to data lines and scan lines;
• a data driver and a scan driver disposed on a same side of a display area, the scan driver being connected to each of the scan lines by a plurality of output signal lines, the data driver including a data driving circuit that comprises:
• an output delay controller configured to control delay times of data signals to be different from each other based on distances between contact points of the scan lines and the output signal lines and the data lines,
• wherein the output delay controller comprises:
• a clock frequency divider which divides a frequency of a data transmission clock to generate a reference clock;
• a reference period generator which generates reference periods for delaying an output of the data signals based on a period of the reference clock;
• a minimum delay selector which selects one of the reference periods as minimum delay value based on the position information;
• and
• a delay time determiner which determines delay times of the first to k-th transmission lines based, on the minimum delay value and a delay control signal, and delays and outputs the data signals by the delay times.