Shift register, driving method therefor, gate driving circuit and display device

A shift register, comprising:

• an input module, a first reset module, a second reset module, and an output module, wherein:
• the input module is coupled respectively with a signal input terminal, a second clock signal terminal, a first node, and a second node, and configured to write an input signal of the signal input terminal into the second node under a control of the second clock signal terminal, and to connect the second node with the first node under a control of the signal input terminal;
• the first reset module is coupled respectively with the signal input terminal, a first DC signal terminal, a reset signal terminal, the first node, the second node, and a third node, and configured to write a signal of the first DC signal terminal into the third node under a control of the signal input terminal, to write a reset signal of the reset signal terminal into the third node under a control of the reset signal terminal, and to connect the second node with the first node;
• the second reset module is coupled respectively with a signal output terminal, the first DC signal terminal, and the third node, and configured to write the signal of the first DC signal terminal into the signal output terminal under a control of the third node;
• and
• the output module is coupled respectively with a first clock signal terminal, the signal output terminal, and the first node, and configured to write a first clock signal of the first clock signal terminal into the signal output terminal under a control of the first node;
• the shift register further comprises an output control module, wherein:
• the output control module is coupled respectively with the first node, the second clock signal terminal, the first DC signal terminal, and a second DC signal terminal;
• and
• the output control module is configured to pull up a level difference between the first node and the signal output terminal under a control of the second DC signal terminal, and to pull down the level difference between the first node and the signal output terminal under a joint control of the second clock signal terminal and the second DC signal terminal;
• or,
• the shift register further comprises an output control module, wherein:
• the output control module is coupled respectively with the first node, the second clock signal terminal, the first DC signal terminal, a second DC signal terminal, and the signal output terminal;
• and
• the output control module is configured to pull up a level difference between the first node and the signal output terminal under the control of the signal output terminal;
• and to pull down a level difference between the first node and the signal output terminal under the control of the second clock signal terminal.