System and method for latency-aware mapping of quantum circuits to quantum chips
AssigneeInternational Business Machines Corporation
InventorsAli Javadiabhari, Scott D. Lekuch, Ken Inoue
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AssigneeInternational Business Machines Corporation
InventorsAli Javadiabhari, Scott D. Lekuch, Ken Inoue
Estimating the term…
A quantum circuit generator for a quantum computer includes a controller; and a plurality of analog conversion units (ACUs) operatively connected to the controller, each ACU being operatively connected to a corresponding qubit of a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits being mapped by the controller and based on latency of the generated quantum circuit so that the generated quantum circuit has a latency less than a threshold latency.
A quantum circuit generator for a quantum computer, comprising:
A quantum computer, comprising:
A method for reducing a latency of a quantum circuit, comprising:
A computer readable medium on which is stored non-transitory computer-executable code, which when executed by a controller causes the controller to:
Dependencies are inferred from the claim text.