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US 11,537,897 B2Granted
Artificial neural network circuit training method, training program, and training device
AssigneeDenso Corporation
InventorIrina Kataeva
Life of this patent
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Abstract
A method for training an artificial neural network circuit is provided. The artificial neural network circuit includes a crossbar circuit that has a plurality of input bars, a plurality of output bars crossing the plurality of input bars, and memristors each of which includes a variable conductance element provided at corresponding one of intersections of the input bars and the output bars.
Claims12
A method for training an artificial neural network circuit, the artificial neural network circuit including
- a crossbar circuit that has:
- a plurality of input bars;
- a plurality of output bars crossing the plurality of input bars;
- and
- memristors each of which includes a variable conductance element provided at corresponding one of intersections of the input bars and the output bars,
- wherein:
- each of the memristors has a characteristic that a conductance is updated in response to a write voltage VWRITE having a magnitude equal to or higher than a write voltage threshold being applied, and that the conductance is maintained in response to a voltage having a magnitude lower than the write voltage threshold being applied;
- a magnitude of the write voltage threshold has a variation with respect to a specified value VTH,
- a memristor in the memristors targeted for an update of the conductance by the write voltage VWRITE is a selected memristor;
- a memristor other than the selected memristor is a non-selected memristor;
- a voltage V50 is applied to an input bar to which one end of the selected memristor is connected;
- a voltage V51 is applied an output bar to which a different end of the selected memristor is connected;
- the method comprising:
- an application voltage setting step that
- sets the voltages V50, V51 to satisfy a relationship of VTH+dV≤|V50−V51|=|VWRITE|≤2(VTH−dV), in which the dV is a voltage meeting a positive margin voltage, in which a magnitude of the margin voltage is set based on a write voltage threshold variation of the memristors, and
- sets voltages applied to an input bar other than the input bar to which the one end of the selected memristor is connected and an output bar other than the output bar to which the different end of the selected memristor is connected to voltages producing a voltage difference smaller than VTH−dV at both ends of the non-selected memristor;
- and
- a voltage applying step that applies the voltages set by the application voltage setting step to the input bars and the output bars with a voltage application device.
15 more elements
Dependencies are inferred from the claim text.