Reduction mode of planar engine in neural processor

A method for operating a neural processor, the method comprising:

• transmitting first input data to at least one of a plurality of neural engine circuits of the neural processor;
• performing, using the at least one of the plurality of neural engine circuits, a convolution operation of the first input data with one or more kernels to generate a first output;
• transmitting second input data to a planar engine circuit, the second input data corresponding to the first output or a version of the first input data of the neural processor;
• performing a reduction operation on a version of the second input data to process a plurality of values arranged in at least a first dimension of the second input data into a first reduced value;
• generating a second output that includes a version of the first reduced value;
• storing the first reduced value to register of the planar engine circuit,
• receiving third input data,
• performing the reduction operation on a version of the third input data to generate a second reduced value, and
• accumulate the second reduced value with the first reduced value in the register, wherein the second output comprises a value accumulated in the register.

An electronic device, comprising:

• a memory storing a machine learning model;
• and
• a neural processor, comprising:
• a plurality of neural engine circuits, at least one of the neural engine circuits configured to perform a convolution operation of first input data with one or more kernels to generate a first output;
• and
• a planar engine circuit coupled to the plurality of neural engine circuits, the planar engine circuit configured to:
• receive second input data corresponding to the first output or a version of the first input data of the neural processor,
• perform a reduction operation on a version of the second input data to process a plurality of values arranged in at least a first dimension of the second input data into a first reduced value, and
• generate a second output that includes a version of the first reduced value wherein the planar engine circuit comprises a first filter circuit programmed as a reduction tree to perform the reduction operation on the version of the second input data.

A neural processor, comprising:

• a plurality of neural engine circuits, at least one of the neural engine circuits configured to perform a convolution operation of first input data with one or more kernels to generate a first output;
• and
• a planar engine circuit coupled to the plurality of neural engine circuits, the planar engine circuit configured to:
• receive second input data corresponding to the first output or a version of the first input data of the neural processor,
• perform a reduction operation on a version of the second input data to process a plurality of values arranged in at least a first dimension of the second input data into a first reduced value, and
• generate a second output that includes a version of the first reduced value, wherein the planar engine circuit comprises a first filter circuit programmed as a reduction tree to perform the reduction operation on the version of the second input data.