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US 11,537,861 B2Granted
Methods of performing processing-in-memory operations, and related devices and systems
AssigneeMicron Technology, Inc.
InventorsDmitri Yudanov, Sean S. Eilert, Hernan A. Castro, William A. Melton
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Abstract
Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and a word line of a number of word lines. A number of signals corresponding to bits of a second number may be driven on the number of word lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.
Claims24
An apparatus, comprising:
- a bit line coupled to a plurality of memory elements of a memory array;
- a first set of word lines intersecting the bit line;
- a first set of memory elements of the plurality at intersections of the bit line and the first set of word lines, the first set of memory elements configured to store ordered bits of a first number;
- a driver configured to drive a first set of signals on the first set of word lines, the first set of signals corresponding to ordered bits of a second number;
- and
- a summing circuit configured to:
- receive a number of output signals from the bit line;
- generate a digital output in response to receipt of an output signal of the number of output signals;
- shift the digital output;
- and
- accumulate the shifted digital output to generate a first value equal to the product of the first number and the second number.
8 more elements
An apparatus, comprising:
- a bit line coupled to a plurality of memory elements of a memory array;
- a first set of word lines intersecting the bit line;
- a first set of memory elements of the plurality at intersections of the bit line and the first set of word lines, the first set of memory elements configured to store bits of a first number;
- a driver configured to drive a first set of signals on the first set of word lines, the first set of signals corresponding to bits of a second number;
- and
- a summing circuit configured to:
- receive a number of output signals from the bit line;
- generate a digital output in response to receipt of an output signal of the number of output signals;
- shift the digital output and
- accumulate the shifted digital output to generate a first value equal to the product of the first number and the second number, wherein the summing circuit comprises:
- a scaling unit configured to:
- receive a first output signal of the number of output signals of the bit line;
- provide a second signal that is a fraction of the first output signal;
- and
- integrate the second signal with a second output signal of the number of output signals of the bit line.
12 more elements
An apparatus, comprising:
- a bit line coupled to a plurality of memory elements of a memory array;
- a first set of word lines intersecting the bit line;
- a first set of memory elements of the plurality at intersections of the bit line and the first set of word lines, the first set of memory elements configured to store bits of a first number;
- a driver configured to drive a first set of signals on the first set of word lines, the first set of signals corresponding to bits of a second number;
- and
- a summing circuit configured to:
- receive a number of output signals from the bit line;
- generate a digital output in response to receipt of an output signal of the number of output signals;
- shift the digital output and
- accumulate the shifted digital output to generate a first value equal to the product of the first number and the second number, wherein the summing circuit comprises:
- a sense amplifier having an input coupled to the bit line;
- a scaling amplifier having at least one input coupled to an output of the sense amplifier;
- a signal divider having an input coupled to an output of the scaling amplifier and an output coupled to the at least one input of the scaling amplifier;
- and
- an analog-to-digital converter (ADC) coupled to the output of the scaling amplifier.
12 more elements
A method, comprising:
- storing ordered bits of a first number in a first set of memory elements that intersect a data line and a first set of access lines;
- driving a first set of signals, which correspond to ordered bits of a second number, on the first set of access lines;
- receiving a number of output signals from the data line;
- generating a digital signal in response to receipt of an output signal of the number of output signals;
- shifting the digital signal;
- and
- accumulating the shifted digital signal to generate a first value equal to the product of the first number and the second number.
4 more elements
A memory system, comprising:
- at least one memory device comprising:
- a bit line;
- a first set of word lines, wherein ordered bits of a first synaptic weight of a first neuron of a neural network layer are stored at respective intersections between the bit line and the first set of word lines;
- a driver configured to drive a first set of signals on the first set of word lines, wherein the input of a neural network layer;
- and
- a summing circuit configured to:
- receive signals via the bit line;
- and
- in response to receiving the signals via the bit line, generate a first value equal to a product of the first synaptic weight and the first input.
6 more elements
A system, comprising:
- at least one input device;
- at least one output device;
- at least one processor device coupled to the input device and the output device;
- and
- at least one memory device coupled to the at least one processor device and comprising:
- a memory array comprising:
- a bit line;
- a number of word lines intersecting the bit line;
- and
- a number of resistive memory elements, each intersection of the bit line and the number of word lines including a resistive memory element of the number of resistive memory elements, wherein ordered bits of a first number are stored in the number of resistive memory elements;
- and
- a driver configured to drive a first set of signals on the number of word lines, the first set of signals corresponding to ordered bits of a second number.
9 more elements
Dependencies are inferred from the claim text.