Low spike count ring buffer mechanism on neuromorphic hardware
AssigneeInternational Business Machines Corporation
InventorAlexander Andreopoulos
Life of this patent
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Abstract
Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.
Claims21
A system comprising:
- a ring buffer comprising a plurality of memory cells, each memory cell of the plurality of memory cells comprising one or more neurosynaptic core;
- a demultiplexer operatively coupled to the ring buffer, the demultiplexer adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells;
- a plurality of output connectors operatively coupled to the ring buffer, each of the plurality of output connectors adapted to provide an output based on contents of a subset of the plurality of memory cells.
A method comprising:
- receiving input comprising a plurality of spikes at a demultiplexer;
- writing by the demultiplexer sequentially to each of a plurality of memory cells of a ring buffer, each memory cell of the plurality of memory cells comprising one or more neurosynaptic core;
- providing an output based on contents of a subset of the plurality of memory cells at a plurality of output connectors.
A system comprising:
- a computing node comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor of the computing node to cause the processor to perform a method comprising:
- receiving input comprising a plurality of spikes at a demultiplexer;
- writing by the demultiplexer sequentially to each of a plurality of memory cells of a ring buffer, each memory cell of the plurality of memory cells comprising one or more neurosynaptic core;
- providing an output based on contents of a subset of the plurality of memory cells at a plurality of output connectors.
Dependencies are inferred from the claim text.