US 11,537,841 B2Granted

System and method for compact neural network modeling of transistors

AssigneeSamsung Electronics Co., Ltd.

InventorsJing Wang, Woosung Choi

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Abstract

A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.

Claims24

Dependent claims

A method for generating a model of a transistor, the method comprising:

initializing, by a computing system, a plurality of hyper-parameters configuring a structure of a neural network;
training, by the computing system, the neural network in accordance with the hyper-parameters and a plurality of training data relating transistor input state values to transistor output state values to compute a plurality of neural network parameters;
determining, by the computing system, whether the transistor output state values of the training data match an output of the neural network;
in response to determining that the transistor output state values do not match the output of the neural network, updating, by the computing system, the hyper-parameters and re-training the neural network based on the updated hyper-parameters;
in response to determining that the transistor output state values of the training data match the output of the neural network, porting, by the computing system, the neural network to a circuit simulation code to generate a ported neural network;
simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output;
determining, by the computing system, whether a turnaround time of the generation of the simulation output is satisfactory;
in response to determining that the turnaround time is unsatisfactory, updating, by the computing system, the hyper-parameters and re-training the neural network based on the updated hyper-parameters;
and
in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.

7 more elements

A system for generating a model of a transistor, the system comprising:

a processor;
and
memory storing instructions that, when executed by the processor, cause the processor to:
initialize a plurality of hyper-parameters configuring a structure of a neural network;
train the neural network in accordance with the hyper-parameters and a plurality of training data relating transistor input state values to transistor output state values to compute a plurality of neural network parameters;
determine whether the transistor output state values of the training data match an output of the neural network;
in response to determining that the transistor output state values do not match the output of the neural network, update the hyper-parameters and re-train the neural network based on the updated hyper-parameters;
in response to determining that the transistor output state values of the training data match the output of the neural network, port the neural network to a circuit simulation code to generate a ported neural network;
simulate a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output;
determine whether a turnaround time of the generation of the simulation output is satisfactory;
in response to determining that the turnaround time is unsatisfactory, update the hyper-parameters and re-train the neural network based on the updated hyper-parameters;
and
in response to determining that the turnaround time is satisfactory, output the ported neural network as the model of the transistor.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/430,219Filed 3 Jun 2019 · us provisional application
Priority: 8 Apr 2019
Published: US 2020/0320366 A18 Oct 2020
Granted: 27 Dec 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06N 3/0464
Architecture, e.g. interconnection topology: convolutional networks [CNN, ConvNet]
G06F 30/27
Design optimisation, verification or simulation: using machine learning, e.g. artificial intelligence, neural networks, support vector machines…
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06N 3/0499
Architecture, e.g. interconnection topology: feedforward networks