Timing and placement co-optimization for engineering change order (ECO) cells

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• access an engineering change order (ECO) for a current design of an integrated circuit, the ECO inserting an ECO cell among placed and routed current cells of the current design;
• identifying a target region in the current design for placement of the ECO cell, but wherein the target region has insufficient open space to place the ECO cell;
• determining slacks for current cells between the target region and current open spaces in the current design;
• and
• based on the slacks of the current cells, construct a chain of moves comprising:
• a first move comprising placing the ECO cell at a location within the target region, thus displacing a current cell;
• and
• a last move comprising moving a current cell displaced in the next-to-last move to one of the current open spaces;
• wherein the ECO cell is a buffer;
• the ECO fixes a violation of a hold timing constraint for a timing path by inserting the buffer along the timing path;
• the timing slacks for the current cells are timing slacks that degrade by increasing routing length for the current cells;
• and each move in the chain of moves is based on not degrading the timing slack so much as to create an additional timing violation for the moved cell.

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• access an engineering change order (ECO) for a current design of an integrated circuit, the ECO inserting an ECO cell among placed and routed current cells of the current design;
• identify a target region in the current design for placement of the ECO cell;
• determine slacks for current cells in a neighborhood of the target region;
• and
• based on the slacks of the current cells, moving at least one of the current cells to a different location to create sufficient open space to place the ECO cell within the target region;
• wherein the ECO cell is a buffer;
• the ECO fixes a violation of a hold timing constraint for a timing path by inserting the buffer along the timing path;
• the timing slacks for the current cells are timing slacks that degrade by increasing routing length for the current cells;
• and moving the at least one current cell to the different location is based on not degrading the timing slack so much as to create an additional timing violation for the moved cell.