Optimized reconfiguration algorithm based on dynamic voltage and frequency scaling

An optimized reconfiguration algorithm based on dynamic voltage and frequency scaling (DVFS), comprising the following steps:

• step 1:
• extracting user task information of user tasks mapped to a field programmable gate array (FPGA) system;
• step 2:
• adjusting running periods of corresponding circuit reconfiguration tasks through an integer linear programming (ILP) method, for each of the user tasks, according to use of an Internet content adaptation protocol (ICAP) module of the FPGA system and importance of a current user task;
• scheduling each of generated circuit reconfiguration tasks to precede corresponding user tasks according to calculated running periods;
• and collecting the circuit reconfiguration tasks and the corresponding user tasks into conflict sets CΛ according to a conflict relationship of the circuit reconfiguration tasks;
• step 3:
• resolving conflicts between the circuit reconfiguration tasks in the conflict sets CΛ obtained in step 2, corresponding to different scenarios, by using one of the following two methods:
• in a scenario that requires high FPGA reliability and is not sensitive to a program running time:
• continuously calling a mixed-integer nonlinear programming (MINLP) optimization solver to solve a nonlinear integer optimization problem, and rescheduling running frequencies of the user tasks and start time of the circuit reconfiguration tasks by using DVFS to maximize stability of the FPGA system;
• and
• in a scenario that requires relatively low FPGA reliability but is sensitive to the program running time:
• designing an approximation algorithm for an original optimization problem based on an approximate DVFS-based scheduling method, and rescheduling the user tasks and the circuit reconfiguration tasks by using DVFS to maximize the stability of the FPGA system while significantly reducing an algorithm running time;
• step 4:
• fine-tuning a schedule generated in step 3 through an Earliest Deadline as Late as possible (EDL) algorithm to obtain a final schedule of the circuit reconfiguration tasks;
• and
• step 5:
• reading scheduling information of each of the user tasks generated in step 4, and continuously reconfiguring a circuit of each of the user tasks to improve the stability of the FPGA system.