Systems and methods for integrated circuit layout
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKenan Yu, Qingwen Deng
Life of this patent
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Abstract
A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.
Claims20
An integrated circuit design implementation system, comprising:
- a first cell library including a plurality of first non-transistor-based cells, each of the plurality of first non-transistor-based cells having no transistor and associated with a respective delay value;
- a synthesis tool configured to:
- receive and synthesize a behavioral description of a circuit design;
- and
- generate a logic gate-level circuit description from the behavioral description;
- a place and route tool configured to generate a layout from the logic gate-level circuit description;
- a timing analysis tool configured to:
- detect a timing violation along a timing path of the layout;
- determine a value of the timing violation;
- and
- access, based on the determination, the first cell library to cause the place and route tool to update the layout by inserting one or more of the plurality of first non-transistor-based cells into the timing path;
- and
- an output tool configured to output the updated layout to a manufacturing tool.
An integrated circuit design implementation system, comprising:
- a first cell library including a plurality of first non-transistor-based cells, each of the plurality of first non-transistor-based cells associated with a respective first delay value;
- a second cell library including a plurality of second transistor-based cells, each of the plurality of second transistor-based cells associated with a respective second delay value;
- a synthesis tool configured to:
- receive and synthesize a behavioral description of a circuit design;
- and
- generate a logic gate-level circuit description from the behavioral description;
- a place and route tool configured to generate a layout from the logic gate-level circuit description;
- a timing analysis tool configured to:
- detect a timing violation along a timing path of the layout;
- determine a value of the timing violation;
- and
- based on the value of the timing violation, update the layout by inserting either one or more of the plurality of first non-transistor-based cells into the timing path or one or more of the plurality of second transistor-based cells into the timing path;
- and
- an output tool configured to output the updated layout to a manufacturing tool.
An integrated circuit design implementation system, comprising:
- a first cell library including a plurality of first non-transistor-based cells, each of the plurality of first non-transistor-based cells associated with a respective first delay value;
- a second cell library including a plurality of second transistor-based cells, each of the plurality of second transistor-based cells associated with a respective second delay value;
- a synthesis tool configured to:
- receive and synthesize a behavioral description of a circuit design;
- and
- generate a logic gate-level circuit description from the behavioral description;
- a place and route tool configured to generate a layout from the logic gate-level circuit description;
- a timing analysis tool configured to:
- detect a timing violation along a timing path of the layout;
- determine a value of the timing violation;
- in response to determining that the value of the timing violation is less than a predefined condition, update the layout by inserting one or more of the plurality of first non-transistor-based cells into the timing path;
- and
- in response to determining that the value of the timing violation is equal to or greater than the predefined condition, update the layout by inserting one or more of the plurality of second transistor-based cells into the timing path;
- and
- an output tool configured to output the updated layout to a manufacturing tool.
Dependencies are inferred from the claim text.