Synchronized clock signals for circuit emulators

A system, comprising:

• a first non-blocking cross-point switch receiving a first plurality of clock inputs and outputting a first plurality of clock outputs;
• a first plurality of buffering devices receiving the first plurality of clock outputs and outputting a first plurality of buffered clock signals, the first plurality of buffered clock signals being synchronized with each other;
• a first plurality of connectors receiving the first plurality of buffered clock signals and outputting a plurality of blade signals;
• and
• a plurality of blades receiving the plurality of blade signals, each blade including a plurality of programmable logic devices, an operation of each programmable logic device being synchronized based on the first plurality of clock inputs.

A system, comprising:

• a first non-blocking cross-point switch receiving a first plurality of clock inputs and outputting a first plurality of clock outputs, the first plurality of clock outputs including a first set of clock outputs and a second set of clock outputs;
• a first set of buffering devices receiving the first set of clock outputs and outputting a first set of buffered clock signals;
• a second set of buffering devices receiving the second set of clock outputs and outputting a second set of buffered clock signals, the first set of buffered clock signals and the second set of buffered clock signals being synchronized with each other;
• a second non-blocking cross-point switch receiving a second plurality of clock inputs and outputting a second plurality of clock outputs, wherein
• the second plurality of clock outputs are provided to the first set of buffering devices,
• the first set of buffering devices outputting a first set of buffered clock signals based on one of the first set of clock outputs and the second plurality of clock outputs, and
• the second set of buffering devices outputting a second set of buffered clock signals based on the second set of clock outputs;
• a first set of connectors receiving the first set of buffered clock signals and outputting a first plurality of blade signals based on the first set of buffered clock signals;
• a second set of connectors receiving the second set of buffered clock signals and outputting a second plurality of blade signals based on the second set of buffered clock signals;
• and
• a plurality of blades receiving the first plurality of blade signals and the second plurality of blade signals, wherein
• each blade includes a plurality of programmable logic devices, and
• an operation of each programmable logic device is synchronized based on one of the first plurality of clock inputs and the second plurality of clock inputs.