SR flip-flop based physical unclonable functions for hardware security

A method for implementing a physical unclonable function device comprising:

• providing an integrated circuit having a plurality of set/reset flip flop logic circuits, wherein each of the plurality of set/reset flip flop logic circuits are a combination of NAND gates, wherein each of the set/reset flip flop logic circuits enters a metastable state for a particular input sequence, wherein the integrated circuit further comprises a plurality of input multiplexers, each of the plurality of input multiplexers being associated with one of the grids of set/reset flip flop logic circuits, wherein each input multiplexer accepts an input comprising three input bits;
• varying circuit parameters of an output NAND gate for each of the plurality of set/reset flip flop logic circuits to account for manufacturing variations in the set/reset flip flop logic circuits and enable generating a stable but random output in response to the particular input sequence;
• applying the particular input sequence to the integrated circuit;
• and
• deriving a unique identifier for the integrated circuit from an output response of the plurality of set/reset flip flop logic circuits, wherein each set/reset flip flop logic circuit generates a single bit of the unique identifier.

A physical unclonable function device comprising:

• an integrated circuit having a plurality of set/reset flip flop logic circuits, wherein each of the set/reset flip flop logic circuits enters a stable but random state for a particular input sequence, wherein the set/reset flip flop logic circuits are a combination of NAND gates, wherein the particular input sequence for a Set and Reset inputs for one of the set/reset flip flop logic circuits is 1/1 followed by 0/0;
• a controller embedded in the integrated circuit to extract a unique identifier for the integrated circuit from an output response of the set/reset flip flop logic circuits, wherein each set/reset flip flop logic circuit generates a single bit of the unique identifier;
• an additional plurality of set/reset flip flop logic circuits that do not receive the particular input sequence and do not generate a single bit for the unique identifier, wherein the plurality of set/reset flip flop logic circuits and the additional plurality of set/reset flip flop logic circuits are arranged in a centroid architecture of grids of set/reset flip logic circuits;
• and
• a plurality of input multiplexers, each of the plurality of input multiplexers being associated with one of the grids of set/reset flip flop logic circuits, wherein each input multiplexer has a three selector bit, of which, two input bits are used to select an set/reset flip flop logic device in a grid and the remaining input bit is used for determining a mode of operation for the integrated circuit between a regular mode of operation and a non-regular mode of operation that generates the unique identifier.