Processing apparatus, semiconductor integrated circuit, and status monitoring method
AssigneeSocionext Inc.
InventorsSeiji Goto, Eiichi Nimoda
Life of this patent
Estimating the term…
Abstract
In a processing apparatus having semiconductor integrated circuits, a first status monitoring circuit included in a first semiconductor integrated circuit is configured to instruct a plurality of second semiconductor integrated circuits to transmit status information indicating statuses of the plurality of second semiconductor integrated circuits. When a second status monitoring circuit included in each of the plurality of second semiconductor integrated circuits receives the instruction for transmission of the corresponding status information, the second status monitoring circuit transmits encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.
Claims20
A processing apparatus comprising:
- a first semiconductor integrated circuit which is a one-chip semiconductor integrated circuit;
- and
- a plurality of second semiconductor integrated circuits each of which is a one-chip semiconductor integrated circuit,
- wherein the first semiconductor integrated circuit includes a first status monitoring circuit configured to instruct the plurality of second semiconductor integrated circuits to transmit status information indicating respective statuses of the plurality of second semiconductor integrated circuits, and
- wherein each of the plurality of second semiconductor integrated circuits includes a second status monitoring circuit configured to transmit, upon receiving an instruction for transmission of the status information, encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.
A semiconductor integrated circuit comprising:
- an interface circuit configured to communicate with a plurality of semiconductor integrated circuits each of which is a one-chip semiconductor integrated circuit;
- a communication circuit configured to instruct the plurality of semiconductor integrated circuit to transmit status information indicating respective statuses of the plurality of semiconductor integrated circuits, individually receive, from the plurality of semiconductor integrated circuits, encrypted information in which the status information is encrypted, and generate the status information by decrypting the encrypted information;
- and
- an output circuit configured to output the status information to an external apparatus,
- wherein the semiconductor integrated circuit is a one-chip semiconductor integrated circuit.
A semiconductor integrated circuit comprising:
- a storage circuit configured to hold status information indicating a status of the semiconductor integrated circuit;
- a control circuit configured to read the status information from the storage circuit;
- an interface circuit configured to communicate with a first semiconductor integrated circuit which is a one-chip semiconductor integrated circuit;
- and
- a communication circuit configured to generate, upon receiving an instruction for transmission of the status information from the first semiconductor integrated circuit, encrypted information in which the status information read from the storage circuit is encrypted and transmit the encrypted information to the first semiconductor integrated circuit
- wherein the semiconductor integrated circuit is a one-chip semiconductor integrated circuit.
A status monitoring method for a processing apparatus including a first semiconductor integrated circuit which is a one-chip semiconductor integrated circuit, and a plurality of second semiconductor integrated circuits each of which is a one-chip semiconductor integrated circuit, the status monitoring method comprising:
- instructing, by a first status monitoring circuit included in the first semiconductor integrated circuit, the plurality of second semiconductor integrated circuits to transmit status information indicating respective statuses of the plurality of second semiconductor integrated circuits;
- and
- transmitting, by a second status monitoring circuit in each of the plurality of second semiconductor integrated circuits, encrypted information in which the status information is encrypted to the first semiconductor integrated circuit, upon receiving an instruction for transmission of the status information.
Dependencies are inferred from the claim text.