Deadlock condition avoidance in a data processing system with a shared slave
AssigneeNXP USA, Inc.
InventorsGary Robert Kerr, Sunny Gupta, Andrew Robertson
Life of this patent
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Abstract
A system and method for controlling deadlock in a processing system includes asserting a deadlock condition indicator when a timer in a timer circuit has passed a predetermined period of time while a first bus master device occupies a port of a bus slave device, and an empty indicator indicates a second bus master is waiting to occupy the port of the bus slave device while the first bus master is occupying the port of the bus slave device. When the deadlock condition indicator is asserted, action can be taken by the processing system to eliminate the deadlock.
Claims19
A processing system comprising:
- a first bus master device;
- a second bus master device;
- a bus slave device accessible by the first and second bus master devices;
- arbitration circuitry coupled between the first and second bus master devices, and the bus slave device;
- a storage element configured to receive, from the arbitration circuitry, an identifier of the first bus master device when the first bus master device begins occupying a port associated with the bus slave device;
- a counter circuit configured to assert a counter expired indicator when a predetermined period of time passes;
- a deadlock condition detection control circuit configured to assert a deadlock condition indicator when the first bus master device continues to occupy the port associated with the bus slave device, the counter expired indicator is asserted, and the second bus master device is waiting to occupy the port associated with the bus slave device;
- and
- a logic element including a first input coupled to receive the identifier from the arbitration circuitry, a second input coupled to receive the identifier in the storage element, and an output providing a counter restart signal to the counter circuit when the first bus master device discontinues occupying the port associated with the bus slave device and the second bus master device begins occupying the port associated with the bus slave device.
A processing system comprising:
- bus master devices;
- bus slave devices;
- arbitration circuitry coupled between the bus master devices and the bus slave devices;
- a master access queue for each of the bus slave devices, each entry of the master access queue indicating whether a first of the bus master devices is accessing a respective one of the bus slave devices while a second of the bus master devices is waiting to access the one of the bus slave devices;
- counter circuits corresponding to each of the bus slave devices, the counter circuits configured to reset to a starting value upon expiration of a specified time period;
- a deadlock condition detection control circuit configured to assert a deadlock condition indicator when the first of the bus master devices is accessing the one of the bus slave devices when one of the counters corresponding to the one of the bus slave devices is reset and an entry in one of the master access queues corresponding to the one of the bus slave devices indicates the second of the bus master devices is waiting to access the one of the bus slave devices.
A method of controlling deadlock in a processing system comprising:
- maintaining a master access queue which stores identifiers of any bus master devices waiting to access a slave device;
- asserting an empty indicator when the master access queue is empty;
- asserting a deadlock condition indicator when:
- a timer in a timer circuit has passed a predetermined period of time while a first bus master device occupies a port of a bus slave device, and
- the empty indicator is not asserted, indicating that a second bus master is waiting to occupy the port of the bus slave device while the first bus master is occupying the port of the bus slave device;
- and
- taking an action to eliminate the deadlock when the deadlock condition indicator is asserted.
Dependencies are inferred from the claim text.