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US 11,537,542 B1Granted
Direct memory access circuitry and method
AssigneeMarvell Asia Pte Ltd
InventorsSyam Prasad, Amarnath Vishwakarma, Chidamber Kulkarni, Prasanna Sukumar
Life of this patent
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Abstract
Disclosed approaches eliminate involving a bus interface in polling by the host computer system and the peripheral component for events to coordinate direct memory access (DMA) transfers. The host polls main memory for DMA events communicated by the peripheral component, and the peripheral component polls local registers for DMA addresses to initiate DMA transfers. DMA transfers are initiated by the host storing main memory addresses in the local registers of the peripheral component, and DMA events generated by the peripheral component are stored in the main memory.
Claims14
A circuit arrangement, comprising:
- a memory circuit;
- a memory controller coupled to the memory circuit and configured to provide read and write access to the memory circuit;
- a host interface circuit configured to be coupled to a host computer system;
- a first register configured for storage of a first buffer address in main memory of the host computer system;
- a direct memory access circuit coupled to the host interface circuit, the memory controller, and the first register, wherein the direct memory access circuit is configured to:
- poll the first register for presence of the first buffer address from which to transfer data from the main memory of the host computer system;
- initiate with the host interface circuit in response to presence of the first buffer address, a first transfer of first data from the first buffer address to the memory circuit;
- and
- initiate with the host interface circuit in response to completion of the first transfer, a write of first event data to the main memory of the host computer system indicating completion of the first transfer.
6 more elements
A method, comprising:
- providing read and write access to data in a memory circuit of an accelerator platform via an accelerator memory controller;
- polling by a direct memory access (DMA) circuit of the accelerator platform, a first register of the accelerator platform for presence of a first buffer address of main memory of a host computer system from which to transfer data;
- initiating by the DMA circuit with a host interface circuit of the accelerator platform, in response to presence of the first buffer address, a first transfer of first data from the first buffer address to the memory circuit of the accelerator platform;
- and
- initiating by the DMA circuit with the host interface circuit, in response to completion of the first transfer, a write to the main memory of the host computer system of first event data that indicates completion of the first transfer.
2 more elements
A system, comprising:
- a processor arrangement;
- a main memory coupled to the processor arrangement, wherein the main memory is configured with instructions that when executed by the processor arrangement cause the processor arrangement to perform operations including:
- for egress direct memory access (DMA) processing:
- allocating a first buffer in the main memory for egress DMA,
- writing egress data to the first buffer, and
- initiating a write of a main memory address of the first buffer to a first register of a peripheral component in response to completion of writing the egress data to the first buffer;
- and
- for ingress DMA processing:
- allocating a second buffer in the main memory for ingress DMA,
- initiating a write of a main memory address of the second buffer to a second register of the peripheral component;
- polling in the main memory, for ingress event data that indicate completion of a transfer of ingress data to the second buffer,
- reading the ingress data from the second buffer in response to presence of the ingress event data, and
- clearing the ingress event data from the main memory after reading the ingress data.
10 more elements
A method, comprising:
- for egress direct memory access (DMA) processing:
- allocating a first buffer in main memory of a host computer system by a processor arrangement of the host computer system for egress DMA,
- writing egress data to the first buffer, and
- initiating a write of a main memory address of the first buffer to a first register of peripheral component in response to completion of writing the egress data to the first buffer;
- and
- for ingress DMA processing:
- allocating a second buffer in the main memory for ingress DMA,
- initiating a write of a main memory address of the second buffer to a second register of the peripheral component,
- polling for ingress event data in the main memory indicating completion of a transfer of ingress data to the second buffer,
- reading the ingress data from the second buffer in response to presence of the ingress event data, and
- clearing the ingress event data from the main memory after reading the ingress data.
8 more elements
Dependencies are inferred from the claim text.