Memory system design using buffer(s) on a mother board
AssigneeRambus Inc.
InventorsChi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
Life of this patent
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Abstract
A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.
Claims20
A system comprising:
- a processor;
- a first data buffer integrated circuit (IC) of a first set of data buffer ICs and a second data buffer IC of the first set of data buffer ICs disposed on a circuit board;
- a first communication channel of a plurality of communication channels electrically coupling the first data buffer IC of the first set of data buffer ICs to a first data buffer device disposed on a first dual in-line memory module (DIMM) of a first plurality of DIMMs and a first data buffer device disposed on a second DIMM of the first plurality of DIMMs;
- a second communication channel of a plurality of communication channels electrically coupling the second data buffer IC of the first set of data buffer ICs to a second data buffer device disposed on the first DIMM of the first plurality of DIMMs and a second data buffer device disposed on the second DIMM of the first plurality of DIMMs;
- and
- a third communication channel of the plurality of communication channels electrically coupling the first set of data buffer ICs to the processor.
A system comprising:
- a first address buffer integrated circuit (IC) disposed on a circuit board;
- a first set of data buffer ICs disposed on the circuit board;
- a first dual in-line memory module (DIMM) comprising a second set of data buffer devices and a second address buffer device, wherein a first data buffer device of the second set of data buffer devices is coupled to a first data buffer IC of the first set of data buffer ICs, wherein a second data buffer device of the second set of data buffer devices is coupled to a second data buffer IC of the first set of data buffer ICs, and wherein the second address buffer device is coupled to the first address buffer IC;
- and
- a second DIMM comprising a third set of data buffer devices and a third address buffer device, wherein a first data buffer device of the third set of data buffer devices is coupled to the first data buffer IC of the first set of data buffer ICs, wherein a second data buffer device of the third set of data buffer devices is coupled to the second data buffer IC of the first set of data buffer ICs, and wherein the third address buffer device is coupled to the first address buffer IC.
A system comprising:
- a processor;
- a first address buffer integrated circuit (IC) disposed on a circuit board and coupled to the processor;
- a first set of data buffer ICs disposed on the circuit board and each coupled to the processor;
- a first dual in-line memory module (DIMM) comprising a second set of data buffer devices and a second address buffer device, wherein a first data buffer device of the second set of data buffer devices is coupled to a first data buffer IC of the first set of data buffer ICs, wherein a second data buffer device of the second set of data buffer devices is coupled to a second data buffer IC of the first set of data buffer ICs, and wherein the second address buffer device is coupled to the first address buffer IC;
- and
- a first bus coupled between the processor and the first DIMM, wherein the processor is to calibrate the second address buffer device using the first bus.
Dependencies are inferred from the claim text.