Acceleration of data between a network and local I/O in a NUMA system
AssigneeSoftiron Limited
InventorAlan Ott
Life of this patent
Estimating the term…
Abstract
A system includes a central processing unit (CPU) including semiconductor dies, wherein each semiconductor die includes processing cores. The system includes a multi-host network interface card (NIC). The NIC includes an external connection interface circuit and CPU interface circuits. The NIC is coupled to an external data source through the external connection interface circuit and to each the semiconductor dies through a respective CPU interface circuit. The NIC is configured to receive data from the external data source for a different peripherals separately connected to semiconductor dies, and route the data for peripherals through respective CPU interface circuits.
Claims20
A system, comprising:
- a central processing unit (CPU) including a plurality of semiconductor dies, each semiconductor die including one or more processing cores;
- a multi-host network interface card (NIC) including an external connection interface circuit and a plurality of CPU interface circuits, wherein the NIC is configured to:
- be communicatively coupled to an external data source through the external connection interface circuit;
- be communicatively coupled to each of the semiconductor dies through a respective CPU interface circuit;
- receive data from the external data source for a first peripheral connected to a first semiconductor die of the CPU;
- and
- receive data from the external data source for a second peripheral connected to a second semiconductor die of the CPU;
- and
- control circuit configured to:
- route the data for the first peripheral through a first CPU interface circuit of the plurality of CPU interface circuits;
- and
- route the data for the second peripheral through a second CPU interface circuit of the plurality of CPU interface circuits.
A method, comprising:
- communicatively coupling a multi-host network interface card (NIC) with a central processing unit (CPU), the NIC including an external connection interface circuit and a plurality of CPU interface circuits, the CPU including a plurality of semiconductor dies, each semiconductor die including one or more processing cores;
- communicatively coupling the NIC to each of the semiconductor dies through a respective CPU interface circuit;
- at the NIC:
- receiving data from the external data source for a first peripheral connected to a first semiconductor die of the CPU;
- and
- receive data from the external data source for a second peripheral connected to a second semiconductor die of the CPU;
- routing the data for the first peripheral through a first CPU interface circuit of the plurality of CPU interface circuits;
- and
- routing the data for the second peripheral through a second CPU interface circuit of the plurality of CPU interface circuits.
Dependencies are inferred from the claim text.