Cache memory that supports tagless addressing

A method of managing retrieval of data by a digital system, wherein the digital system includes at least one processor, circuitry providing a first cache memory and circuitry providing a second cache memory, the method comprising:

• with the at least one processor, receiving memory access requests each accompanied by a respective virtual address;
• with the at least one processor, for each of the memory access requests, translating the respective virtual address to obtain a corresponding main memory address as well as a corresponding cache memory address;
• with the at least one processor, for each of the memory access requests, accessing the circuitry providing the first cache memory to determine if requested data is stored in the first cache memory, wherein accessing the circuitry providing the first cache memory incudes performing a tag checking operation using at least some bits determined responsive to the respective virtual address;
• with the at least one processor, for at least some of the memory access requests corresponding to requested data that is not stored by the first cache memory, using the corresponding cache memory address to directly index the circuitry providing the second cache memory to retrieve requested data from the circuitry providing the second cache memory;
• and
• with the at least one processor, for at least some of the memory access requests corresponding to requested data that is both not stored by the first cache memory and not stored by the second cache memory, using the corresponding main memory address to retrieve requested data from a main memory.