Translating of logical address to determine first and second portions of physical address
AssigneeMicron Technology, Inc.
InventorDavid A. Palmer
Life of this patent
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Abstract
Methods, systems, and devices for data alignment for logical to physical table compression are described. A controller coupled with the memory array may receive a command to access a logical block address associated with a memory device. In some cases, a first portion of a physical address of the memory device associated with the logical block address may be identified. The controller may perform an operation on the logical block address included in the command and identify a second portion of the physical address based on performing the operation. The physical address of the memory device may be accessed based on identifying the first portion and the second portion.
Claims22
An apparatus comprising:
- a memory array;
- and
- a controller coupled with the memory array and configured to cause the apparatus to:
- receive a command to access a logical block address associated with a memory device;
- identify, based at least in part on the logical block address and a logical-to-physical table stored by the memory device, a first portion of a physical address of the memory device associated with the logical block address, wherein the first portion comprises a section of the memory device associated with the logical block address, the section comprising a plurality of pages that are each mapped to one of a plurality of physical addresses;
- perform, based at least in part on receiving the command, an operation on an entirety of the logical block address included in the received command;
- identify, based at least in part on i) performing the operation on the entirety of the logical block address and ii) a size of the section, a second portion of the physical address, wherein the second portion is a first page of the plurality of pages in the section;
- and
- access the physical address of the memory device based at least in part on the first page.
A non-transitory storage medium storing code comprising instructions, which when executed by a processor of an electronic device, cause the electronic device to:
- receive a command to access a logical block address associated with a memory device;
- identify, based at least in part on the logical block address and a logical-to-physical table stored by the memory device, a first portion of a physical address of the memory device associated with the logical block address, wherein the first portion comprises a section of the memory device associated with the logical block address, the section comprising a plurality of pages that are each mapped to one of a plurality of physical addresses;
- perform, based at least in part on receiving the command, an operation on an entirety of the logical block address included in the received command;
- identify, based at least in part on i) performing the operation on the entirety of the logical block address and ii) a size of the section, a second portion of the physical address, wherein the second portion is a first page of the plurality of pages in the section;
- and
- access the physical address of the memory device based at least in part on the first page.
A method, comprising:
- receiving a command to access a logical block address associated with a memory device;
- identifying, based at least in part on the logical block address and a logical-to-physical table stored by the memory device, a first portion of a physical address of the memory device associated with the logical block address, wherein the first portion comprises a section of the memory device associated with the logical block address, the section comprising a plurality of pages that are each mapped to one of a plurality of physical addresses;
- performing, based at least in part on receiving the command, an operation on an entirety of the logical block address included in the received command;
- identifying, based at least in part on i) performing the operation on the entirety of the logical block address and ii) a size of the section, a second portion of the physical address, wherein the second portion is a first page of the plurality of pages in the section;
- and
- accessing the physical address of the memory device based at least in part on the first page.
Dependencies are inferred from the claim text.