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US 11,537,521 B2Granted
Non-volatile dual inline memory module (NVDIMM) for supporting dram cache mode and operation method of NVDIMM
AssigneeSamsung Electronics Co., Ltd.
InventorSunyoung Lim
Life of this patent
Estimating the term…
Abstract
Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.
Claims21
A memory module comprising:
- first internal data lines;
- second internal data lines;
- a volatile memory chip connected to the first internal data lines;
- a non-volatile memory chip connected to the second internal data lines;
- a controller connected to the volatile memory chip and the non-volatile memory chip via the first internal data lines and the second internal data lines, the controller being configured to apply a first command related to first data of the volatile memory chip to the volatile memory chip at a first time, and apply a second command related to second data of the non-volatile memory chip to the non-volatile memory chip at a second time;
- and
- a first data buffer connected to the volatile memory chip and the controller via the first internal data lines, and connected to a second data buffer outside the memory module,
- wherein the controller is further configured to, at a time point when a first latency of the first command and a second latency of the second command coincide with each other whereby the time point occurs after latencies of both the first command and the second command elapse, control the volatile memory chip and the non-volatile memory chip to:
- move the first data from the volatile memory chip to the non-volatile memory chip, wherein the first data is configured by the controller at the time point as a first data chunk of a plurality of data chunks in a cache flush operation, or
- move the second data from the non-volatile memory chip to the volatile memory chip,
- wherein the second data is configured by the controller at the time point as the first data chunk of the plurality of data chunks in a cache fill operation.
8 more elements
A memory module comprising:
- a volatile memory chip;
- a non-volatile memory chip;
- and
- a controller configured to:
- receive, via a command address bus, an address requested for a data access to the non-volatile memory chip,
- receive parity information about the address,
- when providing a cache address related with the address to the volatile memory chip, restore, based on the parity information about the address and the cache address, tag information indicating a cache mapping between the non-volatile memory chip and the volatile memory chip, thereby controlling the volatile memory chip as a cache memory of the non-volatile memory chip, wherein the tag information consists of N bits restored from the parity information, and a pattern of the tag information identifies one area of the non-volatile memory chip, and a ratio of a first total memory of the non-volatile memory chip to a second total memory of the volatile memory chip is about 2{circumflex over ( )}N,
- receive, via the command address bus, a write request directed to the non-volatile memory chip, and
- control, at a time point when a first latency of a read request directed to the volatile memory chip at a first time and a second latency of write request directed to the non-volatile memory chip at a second time coincide with each other whereby the time point occurs after latencies of the read request and the write request elapse and based on the tag information and the cache address and in response to the write request, first data output from the volatile memory chip to be written to the non-volatile memory chip as second data, wherein the first data is configured by the controller at the time point as a first data chunk of a plurality of data chunks in a cache flush operation.
6 more elements
A memory module comprising:
- first internal data lines;
- second internal data lines;
- a volatile memory chip connected to the first internal data lines;
- a non-volatile memory chip connected to the second internal data lines;
- a controller connected to the volatile memory chip and the non-volatile memory chip via the first internal data lines and the second internal data lines, the controller being configured to apply, at a first time, a first command related to first data of the volatile memory chip to the volatile memory chip, and apply, at a second time, a second command related to second data of the non-volatile memory chip to the non-volatile memory chip;
- and
- a first data buffer connected to the volatile memory chip and the controller via the first internal data lines, the first data buffer being connected to a second data buffer outside the memory module,
- wherein the controller is further configured to:
- at the second time, apply the second command before the first data is output to the first internal data lines,
- control the volatile memory chip as a cache memory of the non-volatile memory chip at a time point when a first latency of the first command and a second latency of the second command coincide with each other whereby the time point occurs after latencies of the first command and the second command elapse, and
- move the first data from the volatile memory chip to the non-volatile memory chip, wherein the first data is configured by the controller at the time point as a first data chunk of a plurality of data chunks in a cache flush operation, or move the second data from the non-volatile memory chip to the volatile memory chip, wherein the second data is configured by the controller at the time point as the first data chunk of the plurality of data chunks in a cache fill operation.
8 more elements
Dependencies are inferred from the claim text.