Marking in-flight requests affected by translation entry invalidation in a data processing system

A processing unit for a data processing system, the processing unit comprising:

• an execution unit that executes a memory-referent instruction to calculate a target effective address (EA) of a corresponding memory-referent request;
• an upper level cache including a data array and an EA directory of the data array, wherein the data array includes an entry allocated to the memory-referent request and the EA directory includes a corresponding directory entry specifying the target EA;
• a translation structure that caches address translations;
• a memory management unit that translates EAs to real addresses by reference to the translation structure;
• a queue configured to buffer a plurality of in-flight memory-referent requests including the memory-referent request, wherein the queue buffers the memory-referent request in association with a pointer to the directory entry in the EA directory specifying the target EA;
• translation sequencing logic that is configured to, based on receiving a translation invalidation request requesting invalidation of an address translation in the translation structure:
• walks the EA directory, determines the target EA in the entry matches an address range specified by the translation invalidation request, and, based on determining the match, precisely marks the memory-referent request based on the pointer to the entry buffered in association with the memory-referent request;
• and
• based on the marking, permits the translation invalidation request to complete with reference to the processing unit only after the memory-referent request has drained from the processing unit.

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a processing unit for a data processing system, the processing unit including:
• an execution unit that executes a memory-referent instruction to calculate a target effective address (EA) of a corresponding memory-referent request;
• an upper level cache including a data array and an EA directory of the data array, wherein the data array includes an entry allocated to the memory-referent request and the EA directory includes a corresponding directory entry specifying the target EA;
• a translation structure that caches address translations;
• a memory management unit that translates EAs to real addresses by reference to the translation structure;
• a queue configured to buffer a plurality of in-flight memory-referent requests including the memory-referent request, wherein the queue buffers the memory-referent request in association with a pointer to the directory entry in the EA directory specifying the target EA;
• translation sequencing logic that is configured to, based on receiving a translation invalidation request requesting invalidation of an address translation in the translation structure:
• walks the EA directory, determines the target EA in the entry matches an address range specified by the translation invalidation request, and, based on determining the match, precisely marks the memory-referent request based on the pointer to the entry buffered in association with the memory-referent request;
• and
• based on the marking, permits the translation invalidation request to complete with reference to the processing unit only after the memory-referent request has drained from the processing unit.