Memory device for supporting cache read operation, operating method thereof, and memory system including the same
AssigneeSK hynix Inc.
InventorsGwan Park, Jeong Gil Choi
Life of this patent
Estimating the term…
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AssigneeSK hynix Inc.
InventorsGwan Park, Jeong Gil Choi
Estimating the term…
A memory device comprises: a page buffer including a first and second latch, a control circuit configured to perform reading data of a word line and storing the data in the first latch, perform discharging the word line, perform moving the data of the first latch to the second latch, and perform outputting the data of the second latch to an exterior, and a control logic configured to control the control circuit such that an execution section of the discharge and moving for a first word line at least partially overlap each other when a second or third cache read command is inputted in a section in which the storage or discharge for the first word line is performed in response to a first cache read command for the first word line.
A memory device comprising:
A memory system comprising:
An operating method of a memory device including a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of page buffers coupled to the plurality of bit lines, each page buffer including a first latch and a second latch, the operating method comprising:
Dependencies are inferred from the claim text.