Asynchronous power loss recovery for memory devices
AssigneeMicron Technology, Inc.
InventorsMichael Winterfeld, Steven S. Williams, Alex J. Wesenberg, Johnny A. Lam
Life of this patent
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Abstract
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.
Claims20
A system comprising:
- a memory device;
- and
- a processing device, operatively coupled to the memory device, the processing device to:
- maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory;
- maintain a write count reflecting a number of bytes written to the memory device;
- maintain a cache miss count reflecting a number of cache misses with respect to a cache of the region of the L2P table;
- responsive to determining that the write count exceeds a first threshold value and the cache miss count exceeds a second threshold value, copy the region of the L2P table to a non-volatile memory.
A method comprising:
- maintaining, by a controller managing a memory device, a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory;
- maintain a write count reflecting a number of bytes written to the memory device;
- maintain a cache miss count reflecting a number of cache misses with respect to a cache of the region of the L2P table;
- responsive to determining that the write count exceeds a first threshold value and the cache miss count exceeds a second threshold value, copy the region of the L2P table to a non-volatile memory.
A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to:
- maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory;
- maintain a write count reflecting a number of bytes written to a memory device;
- maintain a cache miss count reflecting a number of cache misses with respect to a cache of the region of the L2P table;
- responsive to determining that the write count exceeds a first threshold value and the cache miss count exceeds a second threshold value, copy the region of the L2P table to a non-volatile memory.
Dependencies are inferred from the claim text.