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US 11,537,505 B2Granted
Forced debug mode entry
AssigneeCadence Design Systems, Inc.
InventorsRobert T. Golla, Matthew B. Smittle
Life of this patent
Estimating the term…
Abstract
The present disclosure is directed to a mechanism for forcing a processor to enter a debug mode. In one embodiment, a processor includes a logic circuit configured to receive a halt request. In response to receiving the halt request while the processor is not in a quiescent state, the logic circuit forces the processor into the quiescent state after a threshold amount of time has elapsed. Processor operation is then halted, and the processor thus becomes accessible for a debugger to perform debug operations.
Claims17
An apparatus comprising:
- a processor including:
- a logic circuit configured to receive a halt request, wherein responsive to receiving the halt request while the processor is not in a quiescent state, the logic circuit is further configured to, after a predetermined amount of time has elapsed from receiving the halt request, force the processor to halt operation by forcing the processor into a quiescent state, wherein a current state of the processor is accessible by a debug circuit in the processor when the processor is halted and in the quiescent state, wherein the logic circuit is further configured to force the processor into a quiescent state by resetting one or more bus interface units.
A method comprising:
- conveying, in a processor and in response to a command received from an external debugger, a halt request from a debug circuit to a retire logic circuit;
- initiating operation of a timer in the retire logic circuit in response to receiving the halt request when the processor is not in a quiescent state;
- in response to the timer indicating a predetermined time threshold has been reached, forcing the processor into the quiescent state;
- and
- providing a halt acknowledgement to the debug circuit in response to receiving the halt request, wherein a current state of the processor is accessible by the debug circuit when the processor is halted and in the quiescent state, wherein forcing the processor into the quiescent state comprises the retire logic circuit canceling one or more pending transactions, wherein canceling the one or more pending transaction comprises resetting one or more bus interface units.
2 more elements
A processor comprising:
- a debug circuit coupled to a debug interface, wherein the debug circuit is configured to generate a request to halt operation of the processor responsive to receiving a command received, through the debug interface, from a debugger external to the processor;
- a timer configured to, if the processor is not in a quiescent state, begin tracking an amount of time elapsed from a time the request was generated;
- and a retire logic circuit configured to, responsive to the timer indicating that a time threshold has been reached, cause the processor to halt operation and enter the quiescent state and further configured to provide, to the debug circuit, an acknowledgement indicating that the processor is in the quiescent state, wherein the retire logic circuit is configured to force the processor into the quiescent state by canceling one or more pending transactions, wherein canceling one or more pending transactions includes the retire logic circuit resetting one or more bus interface circuits.
Dependencies are inferred from the claim text.