Memory, memory system, and operation method of memory
AssigneeSK hynix Inc.
InventorsMunseon Jang, Hoiju Chung
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AssigneeSK hynix Inc.
InventorsMunseon Jang, Hoiju Chung
Estimating the term…
A memory which includes a downlink error correction circuit suitable for correcting an error in data transferred from a memory controller based on a downlink error correction code transferred from the memory controller to produce an error-corrected data so that when an uncorrectable error is detected in the downlink error correction circuit of the memory or when an uncorrectable error is detected in the memory error correction circuit of the memory, the information that there is an uncorrectable error may be transferred to the memory controller in the memory system by using an uncorrectable error signal and an error flag signal, thus, improving the reliability of the memory system.
A memory, comprising:
A memory system, comprising:
A method for operating a memory, comprising:
An operating method of a memory system, the operating method comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
In individual solid state devices: using arrangements adapted for a specific error detection or correction feature
In individual solid state devices: in sector programmable memories, e.g. flash disk
Improving the reliability of storage systems: in relation to data integrity, e.g. data losses, bit errors
Making use of a particular technique: vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more…
About 14 years 8 months of term left · ends 22 Jun 2041 (estimated)
Various embodiments of the present invention relate to a memory and a memory system.
in the early stages of the semiconductor memory device industry, there were many originally good dies on the wafers, which means that memory chips were produced with no defective memory cells through a semiconductor fabrication process. However, as the capacity of memory devices increases, it becomes difficult to fabricate a memory device that does not have any defective memory cells, and nowadays, it may be said that there is substantially no chance that a memory device is fabricated without any defective memory cells. To address the problem, a repair method of including redundant memory cells in a memory device and replacing defective memory cells with the redundant memory cells is being used.
As another method, an error correction circuit (ECC circuit) for correcting errors in a memory system is used to correct errors occurring in memory cells and errors occurring when data are transferred during a read operation and a write operation of the memory system.
FIG. 1 is a block diagram illustrating a memory system 100 according to an embodiment of the present invention.
FIG. 2 is a flowchart describing a write operation of the memory system 100 shown in FIG. 1 according to an embodiment of the present invention.
FIG. 3 is a flowchart describing a read operation of the memory system 100 shown in FIG. 1 according to an embodiment of the present invention.
Various embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
FIG. 1 is a block diagram illustrating a memory system 100 according to an embodiment of the present invention. In FIG. 1, only the portion directly related to data transfer and error correction in the memory system 100 are illustrated.
Referring to FIG. 1, the memory system 100 may include a memory controller 110 and a memory 150.