US 11,537,464 B2 · Host-based error correction

Abstract

Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.

Claims20

Dependent claims

A method, comprising:

receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a non-volatile memory system that is devoid of error correction logic and is coupleable to the host computing system via a peripheral component interconnect express (PCIe) bus;
determining an acceptable error range for the data based at least in part on an application associated with the data;
performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range;
monitoring, by the error correction logic resident on the host computing system, sectors of the memory system to determine a quantity of data accesses incurred by the sectors during operation of the memory system;
and
controlling, by the error correction logic resident on the host computing system, writing of the data to a sector of the memory system that has incurred less than a threshold quantity of data accesses as part of performing a wear leveling operation involving the memory system.

3 more elements

An apparatus, comprising:

an error correction component comprising hardware deployed on a host computing system, wherein the error correction component is configured to execute instructions to:
receive data that comprises a plurality of uncorrected bits from a non-volatile memory device that is devoid of error correction circuitry and that comprises a plurality of self-selecting memory cells coupleable to the host computing system;
determine an acceptable error range for the data based at least in part on an application associated with the data;
perform an initial error correction operation on the data that comprises the plurality of uncorrected bits based at least in part on the acceptable error range;
monitor sectors of the non-volatile memory device that is devoid of the error correction circuitry to determine a quantity of data accesses incurred by the sectors during operation of the memory device that is devoid of the error correction circuitry;
and control writing of the data to a sector of the memory device that is devoid of the error correction circuitry that has incurred less than a threshold quantity of data accesses as part of performing a wear leveling operation involving the memory device that is devoid of the error correction circuitry.

3 more elements

An apparatus, comprising:

a non-volatile memory (NVM) device that is devoid of error correction circuitry and that comprises a plurality of memory cells that have a respective single chalcogenide material that serves as a switch and storage element for each of the memory cells;
and a media controller coupled to the NVM memory device, wherein the media controller is configured to:
request data that comprises a plurality of uncorrected bits from the memory device, wherein the data contains at least one error;
cause the data that comprises the plurality of uncorrected bits to be transferred to error correction logic, wherein the error correction logic comprises circuitry external to the memory device and the media controller;
determine an acceptable error range for the data based at least in part on an application associated with the data;
send a command to the error correction logic to cause an error correction component to initiate an initial error correction operation on the data that comprises the plurality of uncorrected bits based at least in part on the acceptable error range;
send a command to the error correction logic to monitor sectors of the NVM memory device to determine a quantity of data accesses incurred by the sectors during operation of the memory device that is devoid of the error correction logic;
and receive the data to a sector of the NVM memory device that has incurred less than a threshold quantity of data accesses as part of performing a wear leveling operation.

5 more elements

Dependencies are inferred from the claim text.

Host-based error correction

Life of this patent

Host-based error correction

Life of this patent

Abstract

Claims20