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US 11,537,462 B2Granted
Apparatuses and methods for cyclic redundancy calculation for semiconductor device
AssigneeMicron Technology, Inc.
InventorRyo Fujimaki
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.
Claims20
An apparatus comprising:
- a data queue circuit comprising:
- a sampler configured to receive a plurality of data bits and one or more check bits and further configured to provide the plurality of data bits and the one or more check bits to a first output and provide the plurality of data bits to a second output with timing based on an internal clock;
- and
- a cyclic redundancy check (CRC) calculator circuit configured to receive the plurality of data bits and the one or more check bits from the first output of the sampler and further configured to generate a plurality of CRC calculation bits wherein each of the plurality of CRC calculation bits is based on a subset of the plurality of data bits, and wherein one of the CRC calculation bits is based on a portion of the plurality of data bits and the one or more check bits,
- wherein the one or more check bits are based, at least in part, on the portion of the plurality of data bits and on one or more data bits received by another data queue circuit that are different from the plurality of data bits.
2 more elements
An apparatus including:
- a plurality of data queue circuits, each data queue circuit of the plurality of data queue circuits comprising a respective one of a plurality of cyclic redundancy check (CRC) calculator circuits, each respective CRC calculator circuit of the plurality of CRC calculator circuits configured to receive a plurality of data bits and one or more check bits and further configured to generate a plurality of CRC calculation bits, wherein each of the plurality of CRC calculation bits is based on a subset of the plurality of data bits, and wherein one of the plurality of CRC calculation bits is based on a portion of the plurality of data bits and the one or more check bits;
- and a CRC combine circuit configured to receive the plurality of CRC calculation bits from each CRC calculator circuit of the plurality of the CRC calculator circuits, and further configured to generate a result signal based, at least in part, on the plurality of CRC calculation bits, wherein the one or more check bits are based on the portion of the plurality of data bits and on one or more data bits received by each data queue circuit of the plurality of data queue circuits.
An apparatus comprising:
- a first die comprising:
- a plurality of first memory cells;
- a plurality of data queue circuits comprising a plurality of CRC calculator circuits, wherein each CRC calculator circuit of the plurality of CRC calculator circuits in each data queue circuit of the plurality of data queue circuits is configured to receive a corresponding plurality of data bits and one or more corresponding check bits and further configured to generate a corresponding plurality of CRC calculation bits, wherein each of the plurality of CRC calculation bits is based on a subset of the corresponding plurality of data bits and wherein one of the plurality of CRC calculation bits is based on a portion of the plurality of data bits and the one or more check bits;
- and
- a CRC combine circuit configured to receive the corresponding plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further configured to generate a result signal based, at least in part, on the corresponding plurality of CRC calculation bits from the plurality of CRC calculator circuits;
- and
- a second die stacked with the first die, the second die comprising a plurality of second memory cells,
- wherein the one or more corresponding check bits for a first data queue circuit of the plurality of data queue circuits are based, at least in part, on the portion of the plurality of data bits and one or more data bits of the plurality of data bits of a second data queue circuit of the plurality of data queue circuits that are different from the plurality of data bits for the first data queue circuit.
5 more elements
Dependencies are inferred from the claim text.