Wait optimizer for recording an order of first entry into a wait mode by a virtual central processing unit

A method, comprising:

• executing, by a processor, instructions for a hypervisor and a set of virtual CPUs (vCPUs);
• monitoring, by a processing circuit external to the processor and coupled to the processor, a signal from the processor to detect a first entry of a respective vCPU of the set of vCPUs into a respective wait mode from a plurality of entries of the respective vCPU into the respective wait mode within a respective window of time for the respective vCPU while the respective vCPU is waiting to acquire a ticket lock held by another vCPU of the set of vCPUs, the respective window of time for the respective vCPU being initiated by the first entry of the respective vCPU into the respective wait mode, wherein subsequent entries of the plurality of entries of the respective vCPU into the respective wait mode after the first entry are caused by false wake ups;
• recording, by the processing circuit, a time stamp and a ticket lock address associated with the respective vCPU upon only the first entry of the respective vCPU into the respective wait mode within the respective window of time;
• while the respective vCPU is waiting to acquire the ticket lock in the respective wait mode, counting, by the processing circuit, using a respective timer until the respective timer reaches a respective predetermined value determined by the hypervisor;
• and
• upon the respective timer reaching the respective predetermined value, sending an event signal by the processing circuit to the processor to wake up the respective vCPU to compare a first value stored at the ticket lock address with a second value stored in a memory, wherein the first value indicates a now serving ticket number and the second value indicates a ticket number of the respective vCPU, and wherein the respective vCPU acquires the ticket lock when the first value matches the second value stored in the memory.

An integrated circuit, comprising:

• an event monitor circuit configured to monitor a signal from a host processor external to the integrated circuit to detect an entry of a given vCPU of a set of vCPUs executing on the host processor into a wait mode to acquire a ticket lock held by another vCPU of the set of vCPUs;
• a delay register circuit configured to store a value corresponding to an amount of delay to introduce when the given vCPU of the set of vCPUs enters the wait mode;
• a time window register circuit configured to provide a respective window of time for the given vCPU, during which subsequent entries into the wait mode by the given vCPU after a first entry of the given vCPU into the wait mode are ignored, wherein the subsequent entries into the wait mode by the given vCPU after the first entry of the given vCPU into the wait mode are caused by false wake ups;
• a first entry time register circuit configured to record a time stamp corresponding to only the first entry of the given vCPU into the wait mode within the respective window of time for the given vCPU;
• a lock address register circuit configured to store a ticket lock address of the ticket lock that is contended for by the set of vCPUs;
• and
• a timer circuit configured to, while the given vCPU is waiting to acquire the ticket lock in the wait mode, count until a counter value of the timer circuit reaches the value stored in the delay register circuit,
• wherein the integrated circuit is configured to, upon the counter value of the timer circuit reaches the value stored in the delay register circuit, send an event signal to the host processor to wake up the given vCPU to compare a first value stored at the ticket lock address with a second value stored in a memory, wherein the first value indicates a now serving ticket number and the second value indicates a ticket number of the given vCPU, and wherein the given vCPU acquires the ticket lock when the first value matches the second value stored in the memory.