Power management for virtualized computer systems
AssigneeRed Hat, Inc.
InventorMichael Tsirkin
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Abstract
Aspects of the disclosure provide for mechanisms for memory protection of virtual machines in a computer system. A method of the disclosure includes: determining a plurality of host latency times for a plurality of processor power states of a processor of a host computer system; comparing, by a hypervisor executed on the host computer system, each of the host latency times to a target latency time associated with a virtual machine running on the host computer system; mapping the plurality of processor power states to a plurality of host power states in view of the comparison; and providing the host power states to the virtual machine.
Claims18
A power management method for a virtualized computer system, comprising:
- assigning, by a hypervisor, a target latency time to a virtual machine of a plurality of virtual machines running on a host computer system, wherein the target latency time represents a desired response latency time for the virtual machine;
- determining, by the hypervisor, a plurality of host latency times for a plurality of processor power states of a processor of the host computer system;
- comparing, by the hypervisor executed on the host computer system, each host latency time of the plurality of host latency times to the target latency time associated with the virtual machine running on the host computer system;
- for each of the plurality of processor power states, mapping a processor power state of the plurality of processor power states, in view of the comparison, to a host power state of a plurality of host power states implemented by the hypervisor for the virtual machine;
- and
- providing, by the hypervisor, the plurality of host power states to the virtual machine, wherein the virtual machine performs power management for the virtual machine utilizing the plurality of host power states.
A system to perform power management for a virtualized computer system, comprising:
- a memory;
- and
- a processing device operatively coupled to the memory, the processing device to:
- assign a target latency time to a virtual machine of a plurality of virtual machines running on a host computer system, wherein the target latency time represents a desired response latency time for the virtual machine;
- receive, from the virtual machine, a first request to place a processor of the host computer system in a first host power state of a plurality of host power states, wherein the first host power state is mapped to a first host latency time of a plurality of host latency times that is less than the target latency time and wherein the first host power state reflects a first power state of a plurality of power states implemented by a hypervisor for the virtual machine;
- in response to receiving the first request, cause, by a hypervisor executing on the host computer system, the processor to be placed in a first processor power state of a plurality of processor power states corresponding to the first host power state, wherein the first processor power state is associated with a first entry method that does not comprise a virtual machine exit;
- receive a second request to place the processor in a second host power state of the plurality of host power states, wherein the second host power state is mapped to a second host latency time of the plurality of host latency times that is not less than the target latency time and wherein the second host power state reflects a second power state of the plurality of power states implemented by the hypervisor for the virtual machine;
- and
- in response to receiving the second request, cause, by a hypervisor executing on the host computer system, the processor to be placed to a second processor power state associated with a second entry method, wherein the second entry method includes causing the virtual machine to exit to the hypervisor.
A non-transitory machine-readable storage medium including instructions for performing power management by a virtual machine, that, when accessed by a processing device, cause the processing device to:
- determine an idle time for a virtual processor of the virtual machine at least based on historical idle times;
- compare the idle time with a target latency time;
- and
- in response to determining that the idle time is not less than the target latency time, send, to a hypervisor, a request to place a processor of a host computer system in a first host power state of a plurality of host power states, wherein the first host power state is associated with a first entry method that performs a virtual machine exit and wherein the first host power state reflects a power state implemented by the hypervisor for the virtual machine;
- and
- in response to determining that the idle time is less than the target latency time, send, to the hypervisor, a request to place the processor in a second host power state of the plurality of host power states, wherein the second host power state corresponds to a processor power state of the processor of the host computer system, wherein the processor power state is associated with a second host latency time that is less than the target latency time, and wherein the processor power state is associated with an entry method that does not comprise a virtual machine exit.
Dependencies are inferred from the claim text.