Execution elision of intermediate instruction by processor

A computer system comprising one or more processors and one or more computer-readable memories, wherein a first processor of the one or more processors comprises a processor core configured to perform a method comprising:

• consulting first instruction data to determine whether a second instruction has execution data that matches the first instruction data, wherein the first instruction data is from a first instruction;
• in response to determining that the second instruction has execution data that matches the first instruction data, copying, from the first instruction, a data location into the second instruction, wherein the first instruction depends on data that is to be stored at the data location;
• after receiving an availability indication that the data is at the data location, issuing both the first instruction and the second instruction for execution, without requiring issuing of the first instruction before issuing of the second instruction;
• and
• executing the second instruction by using the data location to obtain the data and so as to skip the first instruction.

A processor core comprising one or more hardware facilities comprising:

• at least one execution unit for executing instructions comprising a first instruction, a second instruction, and a prior instruction;
• and
• a physical register file;
• wherein the processor core is capable of performing a method comprising:
• consulting first instruction data to determine whether the second instruction has execution data that matches the first instruction data, wherein the first instruction data is from the first instruction;
• in response to determining that the second instruction has execution data that matches the first instruction data, copying, from the first instruction, a data location into the second instruction, wherein the first instruction depends on data to be stored at the data location;
• after receiving an availability indication that the data is at the data location, issuing both the first instruction and the second instruction for execution, without requiring issuing of the first instruction before issuing of the second instruction;
• and
• executing the second instruction by using the data location to obtain the data and so as to skip the first instruction and by using the at least one execution unit;
• wherein the executing the second instruction comprises using the physical register file.