Trap sub-portions of computer-readable instructions and related systems, methods, and apparatuses

A system, comprising:

• a processing circuit, the processing circuit comprising:
• a processing core including a program counter to cycle through addresses;
• a data storage device including computer-readable instructions stored thereon, the computer-readable instructions including sub-portions of the computer-readable instructions, the sub-portions to instruct the processing core to execute subroutines, the sub-portions including:
• a first sub-portion at a first location within the data storage device indicated by a first address of the addresses;
• first trap sub-portions at first trap locations within the data storage device, the first trap locations indicated by respective first trap addresses of the addresses, the first trap addresses different from the first address by only a single respective bit, the first trap sub-portions to instruct the processing core to execute first trap subroutines to jump to the first address or back to themselves;
• a second sub-portion at a second location within the data storage device indicated by a second address of the addresses, the second address a ones' complement of the first address, the first sub-portion to instruct the processing core to execute a first subroutine to jump to the second address;
• and
• second trap sub-portions at second trap locations within the data storage device, the second trap locations indicated by respective second trap addresses of the addresses, the second trap addresses different from the second address by only a single respective bit, the second trap sub-portions to instruct the processing core to execute second trap subroutines to jump to the second address, to themselves, or to the first address.

A method of operating a processing circuit, the method comprising:

• initiating cycling of addresses in a program counter with a first address corresponding to a first sub-portion of computer-readable instructions stored by a data storage device at a first location;
• executing, responsive to the first address in the program counter and a first type of stuck-at fault of the program counter or of an address bus, a first trap subroutine corresponding to a first trap sub-portion of the computer-readable instructions to jump to the first address or to itself;
• executing, responsive to the first address in the program counter and the address bus being free of the first type of stuck-at fault, a first sub-routine corresponding to the first sub-portion of the computer-readable instructions to jump to a second address corresponding to a second sub-portion of the computer-readable instructions at a second location of the data storage device;
• and
• executing, responsive to the second address in the program counter and a second type of stuck-at fault of the program counter or of the address bus, a second trap subroutine corresponding to a second trap sub-portion of the computer-readable instructions to jump to the second address, to the first address, or to itself.