Back to results
US 11,537,399 B2Granted
Compression assist instructions
AssigneeApple Inc.
InventorsEric Bainville, Ali Sazegari
Life of this patent
Estimating the term…
Abstract
In an embodiment, a processor supports one or more compression assist instructions which may be employed in compression software to improve the performance of the processor when performing compression/decompression. That is, the compression/decompression task may be performed more rapidly and consume less power when the compression assist instructions are employed then when they are not. In some cases, the cost of a more effective, more complex compression algorithm may be reduced to the cost of a less effective, less complex compression algorithm.
Claims20
A processor comprising:
- a register file comprising a plurality of vector registers;
- and
- an execution core coupled to the register file, wherein the execution core is configured to execute a first instruction specifying a first vector operand, a second operand, and a result vector operand, wherein the first vector operand is in a first vector register of the plurality of vector registers, the second operand is in a second register, and the result vector operand is to be written to a third vector register of the plurality of vector registers, wherein the execution core comprises:
- a plurality of shift circuits configured to shift a plurality of variable-sized bit fields from the second operand to vector element positions based on a plurality of vector elements in the first vector operand;
- and
- a plurality of mask circuits coupled to respective ones of the plurality of shift circuits and configured to mask the plurality of variable-sized bit fields based on the plurality of vector elements, resulting in a plurality of extracted variable-sized bit fields in the vector element positions;
- and
- wherein the execution core is configured to write the plurality of extracted variable-sized bit fields as corresponding vector elements in the result vector operand.
5 more elements
A processor comprising:
- a register file comprising a plurality of vector registers;
- and
- an execution core coupled to the register file, wherein the execution core is configured to execute a first instruction specifying a first vector operand, a second operand, and a result operand, wherein the first vector operand is in a first vector register of the plurality of vector registers, the second operand is in a second register, and the result operand is in a third register, wherein the execution core comprises:
- an adder circuit configured to sum vector elements of the first vector operand;
- and
- a shift circuit coupled to the adder circuit and configured to shift a portion of the second operand to remove a number of bits equal to the sum from the adder circuit;
- and
- the execution core is configured to write a remainder of the portion as a corresponding portion of the result operand in the third register responsive to executing the first instruction.
5 more elements
A processor comprising:
- a register file comprising a plurality of vector registers;
- and
- an execution core coupled to the register file, wherein the execution core is configured to execute a first instruction specifying a first vector operand in a first vector register of the plurality of vector registers, a second vector operand in a second vector register of the plurality of vector registers, and a result operand, and wherein the execute core comprises:
- a plurality of shift circuits configured to shift respective vector elements of the first vector operand;
- and
- a plurality of mask circuits coupled to respective shift circuits of the plurality of shift circuits, wherein the plurality of mask circuits are configured to mask the shifted vector elements to generate variable-sized bit fields;
- wherein the execution core is configured to logically OR the variable-sized bit fields to generate a bit stream comprising a plurality of bit fields in adjacent bits;
- and
- wherein the execution core is configured to write bit stream to a first portion of the result operand.
6 more elements
Dependencies are inferred from the claim text.